gen/lib/Target/ARC/ARCGenInstrInfo.inc

reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace ARC {
  enum {
    PHI	= 0,
    INLINEASM	= 1,
    INLINEASM_BR	= 2,
    CFI_INSTRUCTION	= 3,
    EH_LABEL	= 4,
    GC_LABEL	= 5,
    ANNOTATION_LABEL	= 6,
    KILL	= 7,
    EXTRACT_SUBREG	= 8,
    INSERT_SUBREG	= 9,
    IMPLICIT_DEF	= 10,
    SUBREG_TO_REG	= 11,
    COPY_TO_REGCLASS	= 12,
    DBG_VALUE	= 13,
    DBG_LABEL	= 14,
    REG_SEQUENCE	= 15,
    COPY	= 16,
    BUNDLE	= 17,
    LIFETIME_START	= 18,
    LIFETIME_END	= 19,
    STACKMAP	= 20,
    FENTRY_CALL	= 21,
    PATCHPOINT	= 22,
    LOAD_STACK_GUARD	= 23,
    STATEPOINT	= 24,
    LOCAL_ESCAPE	= 25,
    FAULTING_OP	= 26,
    PATCHABLE_OP	= 27,
    PATCHABLE_FUNCTION_ENTER	= 28,
    PATCHABLE_RET	= 29,
    PATCHABLE_FUNCTION_EXIT	= 30,
    PATCHABLE_TAIL_CALL	= 31,
    PATCHABLE_EVENT_CALL	= 32,
    PATCHABLE_TYPED_EVENT_CALL	= 33,
    ICALL_BRANCH_FUNNEL	= 34,
    G_ADD	= 35,
    G_SUB	= 36,
    G_MUL	= 37,
    G_SDIV	= 38,
    G_UDIV	= 39,
    G_SREM	= 40,
    G_UREM	= 41,
    G_AND	= 42,
    G_OR	= 43,
    G_XOR	= 44,
    G_IMPLICIT_DEF	= 45,
    G_PHI	= 46,
    G_FRAME_INDEX	= 47,
    G_GLOBAL_VALUE	= 48,
    G_EXTRACT	= 49,
    G_UNMERGE_VALUES	= 50,
    G_INSERT	= 51,
    G_MERGE_VALUES	= 52,
    G_BUILD_VECTOR	= 53,
    G_BUILD_VECTOR_TRUNC	= 54,
    G_CONCAT_VECTORS	= 55,
    G_PTRTOINT	= 56,
    G_INTTOPTR	= 57,
    G_BITCAST	= 58,
    G_INTRINSIC_TRUNC	= 59,
    G_INTRINSIC_ROUND	= 60,
    G_LOAD	= 61,
    G_SEXTLOAD	= 62,
    G_ZEXTLOAD	= 63,
    G_INDEXED_LOAD	= 64,
    G_INDEXED_SEXTLOAD	= 65,
    G_INDEXED_ZEXTLOAD	= 66,
    G_STORE	= 67,
    G_INDEXED_STORE	= 68,
    G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 69,
    G_ATOMIC_CMPXCHG	= 70,
    G_ATOMICRMW_XCHG	= 71,
    G_ATOMICRMW_ADD	= 72,
    G_ATOMICRMW_SUB	= 73,
    G_ATOMICRMW_AND	= 74,
    G_ATOMICRMW_NAND	= 75,
    G_ATOMICRMW_OR	= 76,
    G_ATOMICRMW_XOR	= 77,
    G_ATOMICRMW_MAX	= 78,
    G_ATOMICRMW_MIN	= 79,
    G_ATOMICRMW_UMAX	= 80,
    G_ATOMICRMW_UMIN	= 81,
    G_ATOMICRMW_FADD	= 82,
    G_ATOMICRMW_FSUB	= 83,
    G_FENCE	= 84,
    G_BRCOND	= 85,
    G_BRINDIRECT	= 86,
    G_INTRINSIC	= 87,
    G_INTRINSIC_W_SIDE_EFFECTS	= 88,
    G_ANYEXT	= 89,
    G_TRUNC	= 90,
    G_CONSTANT	= 91,
    G_FCONSTANT	= 92,
    G_VASTART	= 93,
    G_VAARG	= 94,
    G_SEXT	= 95,
    G_SEXT_INREG	= 96,
    G_ZEXT	= 97,
    G_SHL	= 98,
    G_LSHR	= 99,
    G_ASHR	= 100,
    G_ICMP	= 101,
    G_FCMP	= 102,
    G_SELECT	= 103,
    G_UADDO	= 104,
    G_UADDE	= 105,
    G_USUBO	= 106,
    G_USUBE	= 107,
    G_SADDO	= 108,
    G_SADDE	= 109,
    G_SSUBO	= 110,
    G_SSUBE	= 111,
    G_UMULO	= 112,
    G_SMULO	= 113,
    G_UMULH	= 114,
    G_SMULH	= 115,
    G_FADD	= 116,
    G_FSUB	= 117,
    G_FMUL	= 118,
    G_FMA	= 119,
    G_FMAD	= 120,
    G_FDIV	= 121,
    G_FREM	= 122,
    G_FPOW	= 123,
    G_FEXP	= 124,
    G_FEXP2	= 125,
    G_FLOG	= 126,
    G_FLOG2	= 127,
    G_FLOG10	= 128,
    G_FNEG	= 129,
    G_FPEXT	= 130,
    G_FPTRUNC	= 131,
    G_FPTOSI	= 132,
    G_FPTOUI	= 133,
    G_SITOFP	= 134,
    G_UITOFP	= 135,
    G_FABS	= 136,
    G_FCOPYSIGN	= 137,
    G_FCANONICALIZE	= 138,
    G_FMINNUM	= 139,
    G_FMAXNUM	= 140,
    G_FMINNUM_IEEE	= 141,
    G_FMAXNUM_IEEE	= 142,
    G_FMINIMUM	= 143,
    G_FMAXIMUM	= 144,
    G_GEP	= 145,
    G_PTR_MASK	= 146,
    G_SMIN	= 147,
    G_SMAX	= 148,
    G_UMIN	= 149,
    G_UMAX	= 150,
    G_BR	= 151,
    G_BRJT	= 152,
    G_INSERT_VECTOR_ELT	= 153,
    G_EXTRACT_VECTOR_ELT	= 154,
    G_SHUFFLE_VECTOR	= 155,
    G_CTTZ	= 156,
    G_CTTZ_ZERO_UNDEF	= 157,
    G_CTLZ	= 158,
    G_CTLZ_ZERO_UNDEF	= 159,
    G_CTPOP	= 160,
    G_BSWAP	= 161,
    G_BITREVERSE	= 162,
    G_FCEIL	= 163,
    G_FCOS	= 164,
    G_FSIN	= 165,
    G_FSQRT	= 166,
    G_FFLOOR	= 167,
    G_FRINT	= 168,
    G_FNEARBYINT	= 169,
    G_ADDRSPACE_CAST	= 170,
    G_BLOCK_ADDR	= 171,
    G_JUMP_TABLE	= 172,
    G_DYN_STACKALLOC	= 173,
    ADJCALLSTACKDOWN	= 174,
    ADJCALLSTACKUP	= 175,
    BRcc_rr_p	= 176,
    BRcc_ru6_p	= 177,
    GETFI	= 178,
    STB_FAR	= 179,
    STH_FAR	= 180,
    ST_FAR	= 181,
    ADD_S_limms3	= 182,
    ADD_S_rlimm	= 183,
    ADD_S_rr	= 184,
    ADD_S_rrr	= 185,
    ADD_S_rru6	= 186,
    ADD_S_rs3	= 187,
    ADD_S_ru3	= 188,
    ADD_S_u7	= 189,
    ADD_f_rrlimm	= 190,
    ADD_f_rrr	= 191,
    ADD_f_rrs12	= 192,
    ADD_f_rru6	= 193,
    ADD_rrlimm	= 194,
    ADD_rrr	= 195,
    ADD_rrs12	= 196,
    ADD_rru6	= 197,
    AND_f_rrlimm	= 198,
    AND_f_rrr	= 199,
    AND_f_rrs12	= 200,
    AND_f_rru6	= 201,
    AND_rrlimm	= 202,
    AND_rrr	= 203,
    AND_rrs12	= 204,
    AND_rru6	= 205,
    ASL_S_ru3	= 206,
    ASL_S_ru5	= 207,
    ASL_f_rrlimm	= 208,
    ASL_f_rrr	= 209,
    ASL_f_rrs12	= 210,
    ASL_f_rru6	= 211,
    ASL_rrlimm	= 212,
    ASL_rrr	= 213,
    ASL_rrs12	= 214,
    ASL_rru6	= 215,
    ASR_S_ru3	= 216,
    ASR_S_ru5	= 217,
    ASR_f_rrlimm	= 218,
    ASR_f_rrr	= 219,
    ASR_f_rrs12	= 220,
    ASR_f_rru6	= 221,
    ASR_rrlimm	= 222,
    ASR_rrr	= 223,
    ASR_rrs12	= 224,
    ASR_rru6	= 225,
    BCLR_S_ru5	= 226,
    BEQ_S	= 227,
    BGE_S	= 228,
    BGT_S	= 229,
    BHI_S	= 230,
    BHS_S	= 231,
    BL	= 232,
    BLE_S	= 233,
    BLO_S	= 234,
    BLS_S	= 235,
    BLT_S	= 236,
    BL_S	= 237,
    BMSK_S_ru5	= 238,
    BNE_S	= 239,
    BR	= 240,
    BREQ_S	= 241,
    BRNE_S	= 242,
    BRcc_rr	= 243,
    BRcc_ru6	= 244,
    BSET_S_ru5	= 245,
    BTST_S_ru5	= 246,
    B_S	= 247,
    Bcc	= 248,
    CMP_S_limms3	= 249,
    CMP_S_rlimm	= 250,
    CMP_S_rr	= 251,
    CMP_S_rs3	= 252,
    CMP_S_u7	= 253,
    CMP_rlimm	= 254,
    CMP_rr	= 255,
    CMP_ru6	= 256,
    COMPACT_LD_S	= 257,
    COMPACT_MOV_S_hreg	= 258,
    COMPACT_MOV_S_limm	= 259,
    EI_S	= 260,
    ENTER_S	= 261,
    GEN_ABS_S	= 262,
    GEN_ADD1_S	= 263,
    GEN_ADD2_S	= 264,
    GEN_ADD3_S	= 265,
    GEN_AND_S	= 266,
    GEN_AS1L_S	= 267,
    GEN_AS1R_S	= 268,
    GEN_ASL_S	= 269,
    GEN_ASR_S	= 270,
    GEN_BIC_S	= 271,
    GEN_BRK_S	= 272,
    GEN_EXTB_S	= 273,
    GEN_EXTH_S	= 274,
    GEN_JEQ_S	= 275,
    GEN_JL_S	= 276,
    GEN_JL_S_D	= 277,
    GEN_JNE_S	= 278,
    GEN_J_S	= 279,
    GEN_J_S_D	= 280,
    GEN_J_S_D_BLINK	= 281,
    GEN_LS1R_S	= 282,
    GEN_LSR_S	= 283,
    GEN_MPYUW_S	= 284,
    GEN_MPYW_S	= 285,
    GEN_MPY_S	= 286,
    GEN_NEG_S	= 287,
    GEN_NOP_S	= 288,
    GEN_NOT_S	= 289,
    GEN_OR_S	= 290,
    GEN_SEXB_S	= 291,
    GEN_SEXH_S	= 292,
    GEN_SUB_S	= 293,
    GEN_SUB_S_NE	= 294,
    GEN_SWI_S	= 295,
    GEN_TRAP_S	= 296,
    GEN_TST_S	= 297,
    GEN_UNIMP_S	= 298,
    GEN_XOR_S	= 299,
    GP_ADD_S	= 300,
    GP_LDB_S	= 301,
    GP_LDH_S	= 302,
    GP_LD_S	= 303,
    J	= 304,
    JL	= 305,
    JLI_S	= 306,
    JL_LImm	= 307,
    J_LImm	= 308,
    J_S_BLINK	= 309,
    LDB_AB_rs9	= 310,
    LDB_AW_rs9	= 311,
    LDB_DI_AB_rs9	= 312,
    LDB_DI_AW_rs9	= 313,
    LDB_DI_limm	= 314,
    LDB_DI_rlimm	= 315,
    LDB_DI_rs9	= 316,
    LDB_S_OFF	= 317,
    LDB_S_rrr	= 318,
    LDB_X_AB_rs9	= 319,
    LDB_X_AW_rs9	= 320,
    LDB_X_DI_AB_rs9	= 321,
    LDB_X_DI_AW_rs9	= 322,
    LDB_X_DI_limm	= 323,
    LDB_X_DI_rlimm	= 324,
    LDB_X_DI_rs9	= 325,
    LDB_X_limm	= 326,
    LDB_X_rlimm	= 327,
    LDB_X_rs9	= 328,
    LDB_limm	= 329,
    LDB_rlimm	= 330,
    LDB_rs9	= 331,
    LDH_AB_rs9	= 332,
    LDH_AW_rs9	= 333,
    LDH_DI_AB_rs9	= 334,
    LDH_DI_AW_rs9	= 335,
    LDH_DI_limm	= 336,
    LDH_DI_rlimm	= 337,
    LDH_DI_rs9	= 338,
    LDH_S_OFF	= 339,
    LDH_S_X_OFF	= 340,
    LDH_S_rrr	= 341,
    LDH_X_AB_rs9	= 342,
    LDH_X_AW_rs9	= 343,
    LDH_X_DI_AB_rs9	= 344,
    LDH_X_DI_AW_rs9	= 345,
    LDH_X_DI_limm	= 346,
    LDH_X_DI_rlimm	= 347,
    LDH_X_DI_rs9	= 348,
    LDH_X_limm	= 349,
    LDH_X_rlimm	= 350,
    LDH_X_rs9	= 351,
    LDH_limm	= 352,
    LDH_rlimm	= 353,
    LDH_rs9	= 354,
    LDI_S_u7	= 355,
    LD_AB_rs9	= 356,
    LD_AW_rs9	= 357,
    LD_DI_AB_rs9	= 358,
    LD_DI_AW_rs9	= 359,
    LD_DI_limm	= 360,
    LD_DI_rlimm	= 361,
    LD_DI_rs9	= 362,
    LD_S_AS_rrr	= 363,
    LD_S_OFF	= 364,
    LD_S_rrr	= 365,
    LD_S_s11	= 366,
    LD_limm	= 367,
    LD_rlimm	= 368,
    LD_rs9	= 369,
    LEAVE_S	= 370,
    LSR_S_ru5	= 371,
    LSR_f_rrlimm	= 372,
    LSR_f_rrr	= 373,
    LSR_f_rrs12	= 374,
    LSR_f_rru6	= 375,
    LSR_rrlimm	= 376,
    LSR_rrr	= 377,
    LSR_rrs12	= 378,
    LSR_rru6	= 379,
    MAX_f_rrlimm	= 380,
    MAX_f_rrr	= 381,
    MAX_f_rrs12	= 382,
    MAX_f_rru6	= 383,
    MAX_rrlimm	= 384,
    MAX_rrr	= 385,
    MAX_rrs12	= 386,
    MAX_rru6	= 387,
    MIN_f_rrlimm	= 388,
    MIN_f_rrr	= 389,
    MIN_f_rrs12	= 390,
    MIN_f_rru6	= 391,
    MIN_rrlimm	= 392,
    MIN_rrr	= 393,
    MIN_rrs12	= 394,
    MIN_rru6	= 395,
    MOV_S_NE_rlimm	= 396,
    MOV_S_NE_rr	= 397,
    MOV_S_rs3	= 398,
    MOV_S_s3	= 399,
    MOV_S_u8	= 400,
    MOV_rlimm	= 401,
    MOV_rr	= 402,
    MOV_rs12	= 403,
    MOV_ru6	= 404,
    MOVcc	= 405,
    MPYMU_f_rrlimm	= 406,
    MPYMU_f_rrr	= 407,
    MPYMU_f_rrs12	= 408,
    MPYMU_f_rru6	= 409,
    MPYMU_rrlimm	= 410,
    MPYMU_rrr	= 411,
    MPYMU_rrs12	= 412,
    MPYMU_rru6	= 413,
    MPYM_f_rrlimm	= 414,
    MPYM_f_rrr	= 415,
    MPYM_f_rrs12	= 416,
    MPYM_f_rru6	= 417,
    MPYM_rrlimm	= 418,
    MPYM_rrr	= 419,
    MPYM_rrs12	= 420,
    MPYM_rru6	= 421,
    MPY_f_rrlimm	= 422,
    MPY_f_rrr	= 423,
    MPY_f_rrs12	= 424,
    MPY_f_rru6	= 425,
    MPY_rrlimm	= 426,
    MPY_rrr	= 427,
    MPY_rrs12	= 428,
    MPY_rru6	= 429,
    OR_f_rrlimm	= 430,
    OR_f_rrr	= 431,
    OR_f_rrs12	= 432,
    OR_f_rru6	= 433,
    OR_rrlimm	= 434,
    OR_rrr	= 435,
    OR_rrs12	= 436,
    OR_rru6	= 437,
    PCL_LD	= 438,
    POP_S_BLINK	= 439,
    POP_S_r	= 440,
    PUSH_S_BLINK	= 441,
    PUSH_S_r	= 442,
    ROR_f_rrlimm	= 443,
    ROR_f_rrr	= 444,
    ROR_f_rrs12	= 445,
    ROR_f_rru6	= 446,
    ROR_rrlimm	= 447,
    ROR_rrr	= 448,
    ROR_rrs12	= 449,
    ROR_rru6	= 450,
    SETEQ_f_rrlimm	= 451,
    SETEQ_f_rrr	= 452,
    SETEQ_f_rrs12	= 453,
    SETEQ_f_rru6	= 454,
    SETEQ_rrlimm	= 455,
    SETEQ_rrr	= 456,
    SETEQ_rrs12	= 457,
    SETEQ_rru6	= 458,
    SEXB_f_rr	= 459,
    SEXB_rr	= 460,
    SEXH_f_rr	= 461,
    SEXH_rr	= 462,
    SP_ADD_S	= 463,
    SP_ADD_SP_S	= 464,
    SP_LDB_S	= 465,
    SP_LD_S	= 466,
    SP_STB_S	= 467,
    SP_ST_S	= 468,
    SP_SUB_SP_S	= 469,
    STB_AB_rs9	= 470,
    STB_AW_rs9	= 471,
    STB_DI_AB_rs9	= 472,
    STB_DI_AW_rs9	= 473,
    STB_DI_limm	= 474,
    STB_DI_rs9	= 475,
    STB_S_OFF	= 476,
    STB_limm	= 477,
    STB_rs9	= 478,
    STH_AB_rs9	= 479,
    STH_AW_rs9	= 480,
    STH_DI_AB_rs9	= 481,
    STH_DI_AW_rs9	= 482,
    STH_DI_limm	= 483,
    STH_DI_rs9	= 484,
    STH_S_OFF	= 485,
    STH_limm	= 486,
    STH_rs9	= 487,
    ST_AB_rs9	= 488,
    ST_AW_rs9	= 489,
    ST_DI_AB_rs9	= 490,
    ST_DI_AW_rs9	= 491,
    ST_DI_limm	= 492,
    ST_DI_rs9	= 493,
    ST_S_OFF	= 494,
    ST_S_s11	= 495,
    ST_limm	= 496,
    ST_rs9	= 497,
    SUB1_f_rrlimm	= 498,
    SUB1_f_rrr	= 499,
    SUB1_f_rrs12	= 500,
    SUB1_f_rru6	= 501,
    SUB1_rrlimm	= 502,
    SUB1_rrr	= 503,
    SUB1_rrs12	= 504,
    SUB1_rru6	= 505,
    SUB2_f_rrlimm	= 506,
    SUB2_f_rrr	= 507,
    SUB2_f_rrs12	= 508,
    SUB2_f_rru6	= 509,
    SUB2_rrlimm	= 510,
    SUB2_rrr	= 511,
    SUB2_rrs12	= 512,
    SUB2_rru6	= 513,
    SUB3_f_rrlimm	= 514,
    SUB3_f_rrr	= 515,
    SUB3_f_rrs12	= 516,
    SUB3_f_rru6	= 517,
    SUB3_rrlimm	= 518,
    SUB3_rrr	= 519,
    SUB3_rrs12	= 520,
    SUB3_rru6	= 521,
    SUB_S_rrr	= 522,
    SUB_S_ru3	= 523,
    SUB_S_ru5	= 524,
    SUB_f_rrlimm	= 525,
    SUB_f_rrr	= 526,
    SUB_f_rrs12	= 527,
    SUB_f_rru6	= 528,
    SUB_rrlimm	= 529,
    SUB_rrr	= 530,
    SUB_rrs12	= 531,
    SUB_rru6	= 532,
    XOR_f_rrlimm	= 533,
    XOR_f_rrr	= 534,
    XOR_f_rrs12	= 535,
    XOR_f_rru6	= 536,
    XOR_rrlimm	= 537,
    XOR_rrr	= 538,
    XOR_rrs12	= 539,
    XOR_rru6	= 540,
    INSTRUCTION_LIST_END = 541
  };

} // end namespace ARC
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace ARC {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };
} // end namespace Sched
} // end namespace ARC
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static const MCPhysReg ImplicitList1[] = { ARC::SP, 0 };
static const MCPhysReg ImplicitList2[] = { ARC::STATUS32, 0 };
static const MCPhysReg ImplicitList3[] = { ARC::BLINK, 0 };
static const MCPhysReg ImplicitList4[] = { ARC::BLINK, ARC::SP, 0 };

static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, };
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo38[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo39[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo41[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo42[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo43[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo44[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo45[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo46[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo47[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
static const MCOperandInfo OperandInfo49[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
static const MCOperandInfo OperandInfo50[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo51[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo52[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo53[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo54[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo55[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };

extern const MCInstrDesc ARCInsts[] = {
  { 0,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
  { 1,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
  { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
  { 3,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = CFI_INSTRUCTION
  { 4,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = EH_LABEL
  { 5,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = GC_LABEL
  { 6,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = ANNOTATION_LABEL
  { 7,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #7 = KILL
  { 8,	3,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #8 = EXTRACT_SUBREG
  { 9,	4,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #9 = INSERT_SUBREG
  { 10,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #10 = IMPLICIT_DEF
  { 11,	4,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #11 = SUBREG_TO_REG
  { 12,	3,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #12 = COPY_TO_REGCLASS
  { 13,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #13 = DBG_VALUE
  { 14,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #14 = DBG_LABEL
  { 15,	2,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = REG_SEQUENCE
  { 16,	2,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #16 = COPY
  { 17,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #17 = BUNDLE
  { 18,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_START
  { 19,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #19 = LIFETIME_END
  { 20,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #20 = STACKMAP
  { 21,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #21 = FENTRY_CALL
  { 22,	6,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #22 = PATCHPOINT
  { 23,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #23 = LOAD_STACK_GUARD
  { 24,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #24 = STATEPOINT
  { 25,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #25 = LOCAL_ESCAPE
  { 26,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = FAULTING_OP
  { 27,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_OP
  { 28,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_ENTER
  { 29,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_RET
  { 30,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_FUNCTION_EXIT
  { 31,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #31 = PATCHABLE_TAIL_CALL
  { 32,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #32 = PATCHABLE_EVENT_CALL
  { 33,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
  { 34,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #34 = ICALL_BRANCH_FUNNEL
  { 35,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_ADD
  { 36,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_SUB
  { 37,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_MUL
  { 38,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_SDIV
  { 39,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_UDIV
  { 40,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_SREM
  { 41,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_UREM
  { 42,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_AND
  { 43,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_OR
  { 44,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #44 = G_XOR
  { 45,	1,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_IMPLICIT_DEF
  { 46,	1,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #46 = G_PHI
  { 47,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_FRAME_INDEX
  { 48,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #48 = G_GLOBAL_VALUE
  { 49,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #49 = G_EXTRACT
  { 50,	2,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_UNMERGE_VALUES
  { 51,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #51 = G_INSERT
  { 52,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_MERGE_VALUES
  { 53,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_BUILD_VECTOR
  { 54,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BUILD_VECTOR_TRUNC
  { 55,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_CONCAT_VECTORS
  { 56,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_PTRTOINT
  { 57,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_INTTOPTR
  { 58,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_BITCAST
  { 59,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_INTRINSIC_TRUNC
  { 60,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #60 = G_INTRINSIC_ROUND
  { 61,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #61 = G_LOAD
  { 62,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #62 = G_SEXTLOAD
  { 63,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #63 = G_ZEXTLOAD
  { 64,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #64 = G_INDEXED_LOAD
  { 65,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #65 = G_INDEXED_SEXTLOAD
  { 66,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #66 = G_INDEXED_ZEXTLOAD
  { 67,	2,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #67 = G_STORE
  { 68,	5,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #68 = G_INDEXED_STORE
  { 69,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
  { 70,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #70 = G_ATOMIC_CMPXCHG
  { 71,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_XCHG
  { 72,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_ADD
  { 73,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_SUB
  { 74,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #74 = G_ATOMICRMW_AND
  { 75,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #75 = G_ATOMICRMW_NAND
  { 76,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #76 = G_ATOMICRMW_OR
  { 77,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #77 = G_ATOMICRMW_XOR
  { 78,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #78 = G_ATOMICRMW_MAX
  { 79,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #79 = G_ATOMICRMW_MIN
  { 80,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #80 = G_ATOMICRMW_UMAX
  { 81,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #81 = G_ATOMICRMW_UMIN
  { 82,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #82 = G_ATOMICRMW_FADD
  { 83,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #83 = G_ATOMICRMW_FSUB
  { 84,	2,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #84 = G_FENCE
  { 85,	2,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #85 = G_BRCOND
  { 86,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #86 = G_BRINDIRECT
  { 87,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #87 = G_INTRINSIC
  { 88,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
  { 89,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #89 = G_ANYEXT
  { 90,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #90 = G_TRUNC
  { 91,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #91 = G_CONSTANT
  { 92,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #92 = G_FCONSTANT
  { 93,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #93 = G_VASTART
  { 94,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #94 = G_VAARG
  { 95,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #95 = G_SEXT
  { 96,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #96 = G_SEXT_INREG
  { 97,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #97 = G_ZEXT
  { 98,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #98 = G_SHL
  { 99,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #99 = G_LSHR
  { 100,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #100 = G_ASHR
  { 101,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #101 = G_ICMP
  { 102,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #102 = G_FCMP
  { 103,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #103 = G_SELECT
  { 104,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #104 = G_UADDO
  { 105,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #105 = G_UADDE
  { 106,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #106 = G_USUBO
  { 107,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #107 = G_USUBE
  { 108,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #108 = G_SADDO
  { 109,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #109 = G_SADDE
  { 110,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #110 = G_SSUBO
  { 111,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #111 = G_SSUBE
  { 112,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #112 = G_UMULO
  { 113,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #113 = G_SMULO
  { 114,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #114 = G_UMULH
  { 115,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #115 = G_SMULH
  { 116,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #116 = G_FADD
  { 117,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #117 = G_FSUB
  { 118,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #118 = G_FMUL
  { 119,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #119 = G_FMA
  { 120,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #120 = G_FMAD
  { 121,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #121 = G_FDIV
  { 122,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #122 = G_FREM
  { 123,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #123 = G_FPOW
  { 124,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #124 = G_FEXP
  { 125,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #125 = G_FEXP2
  { 126,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #126 = G_FLOG
  { 127,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #127 = G_FLOG2
  { 128,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #128 = G_FLOG10
  { 129,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_FNEG
  { 130,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #130 = G_FPEXT
  { 131,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #131 = G_FPTRUNC
  { 132,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #132 = G_FPTOSI
  { 133,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #133 = G_FPTOUI
  { 134,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #134 = G_SITOFP
  { 135,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_UITOFP
  { 136,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #136 = G_FABS
  { 137,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #137 = G_FCOPYSIGN
  { 138,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #138 = G_FCANONICALIZE
  { 139,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #139 = G_FMINNUM
  { 140,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #140 = G_FMAXNUM
  { 141,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #141 = G_FMINNUM_IEEE
  { 142,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #142 = G_FMAXNUM_IEEE
  { 143,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #143 = G_FMINIMUM
  { 144,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #144 = G_FMAXIMUM
  { 145,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #145 = G_GEP
  { 146,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #146 = G_PTR_MASK
  { 147,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #147 = G_SMIN
  { 148,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #148 = G_SMAX
  { 149,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #149 = G_UMIN
  { 150,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #150 = G_UMAX
  { 151,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #151 = G_BR
  { 152,	3,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #152 = G_BRJT
  { 153,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #153 = G_INSERT_VECTOR_ELT
  { 154,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #154 = G_EXTRACT_VECTOR_ELT
  { 155,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #155 = G_SHUFFLE_VECTOR
  { 156,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #156 = G_CTTZ
  { 157,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #157 = G_CTTZ_ZERO_UNDEF
  { 158,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #158 = G_CTLZ
  { 159,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #159 = G_CTLZ_ZERO_UNDEF
  { 160,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #160 = G_CTPOP
  { 161,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #161 = G_BSWAP
  { 162,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #162 = G_BITREVERSE
  { 163,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #163 = G_FCEIL
  { 164,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #164 = G_FCOS
  { 165,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #165 = G_FSIN
  { 166,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #166 = G_FSQRT
  { 167,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #167 = G_FFLOOR
  { 168,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #168 = G_FRINT
  { 169,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #169 = G_FNEARBYINT
  { 170,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #170 = G_ADDRSPACE_CAST
  { 171,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #171 = G_BLOCK_ADDR
  { 172,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #172 = G_JUMP_TABLE
  { 173,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #173 = G_DYN_STACKALLOC
  { 174,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #174 = ADJCALLSTACKDOWN
  { 175,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #175 = ADJCALLSTACKUP
  { 176,	4,	0,	8,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #176 = BRcc_rr_p
  { 177,	4,	0,	8,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #177 = BRcc_ru6_p
  { 178,	3,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #178 = GETFI
  { 179,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #179 = STB_FAR
  { 180,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #180 = STH_FAR
  { 181,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #181 = ST_FAR
  { 182,	2,	0,	6,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #182 = ADD_S_limms3
  { 183,	2,	1,	6,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #183 = ADD_S_rlimm
  { 184,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #184 = ADD_S_rr
  { 185,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #185 = ADD_S_rrr
  { 186,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #186 = ADD_S_rru6
  { 187,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #187 = ADD_S_rs3
  { 188,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #188 = ADD_S_ru3
  { 189,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #189 = ADD_S_u7
  { 190,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #190 = ADD_f_rrlimm
  { 191,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #191 = ADD_f_rrr
  { 192,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #192 = ADD_f_rrs12
  { 193,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #193 = ADD_f_rru6
  { 194,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #194 = ADD_rrlimm
  { 195,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #195 = ADD_rrr
  { 196,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #196 = ADD_rrs12
  { 197,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #197 = ADD_rru6
  { 198,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #198 = AND_f_rrlimm
  { 199,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #199 = AND_f_rrr
  { 200,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #200 = AND_f_rrs12
  { 201,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #201 = AND_f_rru6
  { 202,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #202 = AND_rrlimm
  { 203,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #203 = AND_rrr
  { 204,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #204 = AND_rrs12
  { 205,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #205 = AND_rru6
  { 206,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #206 = ASL_S_ru3
  { 207,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #207 = ASL_S_ru5
  { 208,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #208 = ASL_f_rrlimm
  { 209,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #209 = ASL_f_rrr
  { 210,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #210 = ASL_f_rrs12
  { 211,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #211 = ASL_f_rru6
  { 212,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #212 = ASL_rrlimm
  { 213,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #213 = ASL_rrr
  { 214,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #214 = ASL_rrs12
  { 215,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #215 = ASL_rru6
  { 216,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #216 = ASR_S_ru3
  { 217,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #217 = ASR_S_ru5
  { 218,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #218 = ASR_f_rrlimm
  { 219,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #219 = ASR_f_rrr
  { 220,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #220 = ASR_f_rrs12
  { 221,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #221 = ASR_f_rru6
  { 222,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #222 = ASR_rrlimm
  { 223,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #223 = ASR_rrr
  { 224,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #224 = ASR_rrs12
  { 225,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #225 = ASR_rru6
  { 226,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #226 = BCLR_S_ru5
  { 227,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #227 = BEQ_S
  { 228,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #228 = BGE_S
  { 229,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #229 = BGT_S
  { 230,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #230 = BHI_S
  { 231,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #231 = BHS_S
  { 232,	1,	0,	4,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList3, OperandInfo48, -1 ,nullptr },  // Inst #232 = BL
  { 233,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #233 = BLE_S
  { 234,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #234 = BLO_S
  { 235,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #235 = BLS_S
  { 236,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #236 = BLT_S
  { 237,	1,	0,	2,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #237 = BL_S
  { 238,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #238 = BMSK_S_ru5
  { 239,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #239 = BNE_S
  { 240,	1,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #240 = BR
  { 241,	2,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #241 = BREQ_S
  { 242,	2,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #242 = BRNE_S
  { 243,	4,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #243 = BRcc_rr
  { 244,	4,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #244 = BRcc_ru6
  { 245,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #245 = BSET_S_ru5
  { 246,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #246 = BTST_S_ru5
  { 247,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #247 = B_S
  { 248,	2,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #248 = Bcc
  { 249,	2,	0,	6,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #249 = CMP_S_limms3
  { 250,	2,	1,	6,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #250 = CMP_S_rlimm
  { 251,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #251 = CMP_S_rr
  { 252,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #252 = CMP_S_rs3
  { 253,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #253 = CMP_S_u7
  { 254,	2,	0,	8,	0,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr },  // Inst #254 = CMP_rlimm
  { 255,	2,	0,	4,	0,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo42, -1 ,nullptr },  // Inst #255 = CMP_rr
  { 256,	2,	0,	4,	0,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr },  // Inst #256 = CMP_ru6
  { 257,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #257 = COMPACT_LD_S
  { 258,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #258 = COMPACT_MOV_S_hreg
  { 259,	2,	1,	6,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #259 = COMPACT_MOV_S_limm
  { 260,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #260 = EI_S
  { 261,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #261 = ENTER_S
  { 262,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #262 = GEN_ABS_S
  { 263,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #263 = GEN_ADD1_S
  { 264,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #264 = GEN_ADD2_S
  { 265,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #265 = GEN_ADD3_S
  { 266,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #266 = GEN_AND_S
  { 267,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #267 = GEN_AS1L_S
  { 268,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #268 = GEN_AS1R_S
  { 269,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #269 = GEN_ASL_S
  { 270,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #270 = GEN_ASR_S
  { 271,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #271 = GEN_BIC_S
  { 272,	0,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #272 = GEN_BRK_S
  { 273,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #273 = GEN_EXTB_S
  { 274,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #274 = GEN_EXTH_S
  { 275,	0,	0,	2,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #275 = GEN_JEQ_S
  { 276,	1,	0,	2,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #276 = GEN_JL_S
  { 277,	1,	0,	2,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #277 = GEN_JL_S_D
  { 278,	0,	0,	2,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #278 = GEN_JNE_S
  { 279,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #279 = GEN_J_S
  { 280,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #280 = GEN_J_S_D
  { 281,	0,	0,	2,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #281 = GEN_J_S_D_BLINK
  { 282,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #282 = GEN_LS1R_S
  { 283,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #283 = GEN_LSR_S
  { 284,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #284 = GEN_MPYUW_S
  { 285,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #285 = GEN_MPYW_S
  { 286,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #286 = GEN_MPY_S
  { 287,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #287 = GEN_NEG_S
  { 288,	0,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #288 = GEN_NOP_S
  { 289,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #289 = GEN_NOT_S
  { 290,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #290 = GEN_OR_S
  { 291,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #291 = GEN_SEXB_S
  { 292,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #292 = GEN_SEXH_S
  { 293,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #293 = GEN_SUB_S
  { 294,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #294 = GEN_SUB_S_NE
  { 295,	0,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #295 = GEN_SWI_S
  { 296,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #296 = GEN_TRAP_S
  { 297,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #297 = GEN_TST_S
  { 298,	0,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #298 = GEN_UNIMP_S
  { 299,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #299 = GEN_XOR_S
  { 300,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #300 = GP_ADD_S
  { 301,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #301 = GP_LDB_S
  { 302,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #302 = GP_LDH_S
  { 303,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #303 = GP_LD_S
  { 304,	1,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #304 = J
  { 305,	1,	0,	4,	0,	0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList3, OperandInfo52, -1 ,nullptr },  // Inst #305 = JL
  { 306,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #306 = JLI_S
  { 307,	1,	0,	8,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #307 = JL_LImm
  { 308,	1,	0,	8,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #308 = J_LImm
  { 309,	0,	0,	2,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #309 = J_S_BLINK
  { 310,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #310 = LDB_AB_rs9
  { 311,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #311 = LDB_AW_rs9
  { 312,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #312 = LDB_DI_AB_rs9
  { 313,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #313 = LDB_DI_AW_rs9
  { 314,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #314 = LDB_DI_limm
  { 315,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #315 = LDB_DI_rlimm
  { 316,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #316 = LDB_DI_rs9
  { 317,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #317 = LDB_S_OFF
  { 318,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #318 = LDB_S_rrr
  { 319,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #319 = LDB_X_AB_rs9
  { 320,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #320 = LDB_X_AW_rs9
  { 321,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #321 = LDB_X_DI_AB_rs9
  { 322,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #322 = LDB_X_DI_AW_rs9
  { 323,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #323 = LDB_X_DI_limm
  { 324,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #324 = LDB_X_DI_rlimm
  { 325,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #325 = LDB_X_DI_rs9
  { 326,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #326 = LDB_X_limm
  { 327,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #327 = LDB_X_rlimm
  { 328,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #328 = LDB_X_rs9
  { 329,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #329 = LDB_limm
  { 330,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #330 = LDB_rlimm
  { 331,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #331 = LDB_rs9
  { 332,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #332 = LDH_AB_rs9
  { 333,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #333 = LDH_AW_rs9
  { 334,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #334 = LDH_DI_AB_rs9
  { 335,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #335 = LDH_DI_AW_rs9
  { 336,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #336 = LDH_DI_limm
  { 337,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #337 = LDH_DI_rlimm
  { 338,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #338 = LDH_DI_rs9
  { 339,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #339 = LDH_S_OFF
  { 340,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #340 = LDH_S_X_OFF
  { 341,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #341 = LDH_S_rrr
  { 342,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #342 = LDH_X_AB_rs9
  { 343,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #343 = LDH_X_AW_rs9
  { 344,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #344 = LDH_X_DI_AB_rs9
  { 345,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #345 = LDH_X_DI_AW_rs9
  { 346,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #346 = LDH_X_DI_limm
  { 347,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #347 = LDH_X_DI_rlimm
  { 348,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #348 = LDH_X_DI_rs9
  { 349,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #349 = LDH_X_limm
  { 350,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #350 = LDH_X_rlimm
  { 351,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #351 = LDH_X_rs9
  { 352,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #352 = LDH_limm
  { 353,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #353 = LDH_rlimm
  { 354,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #354 = LDH_rs9
  { 355,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #355 = LDI_S_u7
  { 356,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #356 = LD_AB_rs9
  { 357,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #357 = LD_AW_rs9
  { 358,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #358 = LD_DI_AB_rs9
  { 359,	4,	2,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #359 = LD_DI_AW_rs9
  { 360,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #360 = LD_DI_limm
  { 361,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #361 = LD_DI_rlimm
  { 362,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #362 = LD_DI_rs9
  { 363,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #363 = LD_S_AS_rrr
  { 364,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #364 = LD_S_OFF
  { 365,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #365 = LD_S_rrr
  { 366,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #366 = LD_S_s11
  { 367,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #367 = LD_limm
  { 368,	3,	1,	8,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #368 = LD_rlimm
  { 369,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #369 = LD_rs9
  { 370,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #370 = LEAVE_S
  { 371,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #371 = LSR_S_ru5
  { 372,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #372 = LSR_f_rrlimm
  { 373,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #373 = LSR_f_rrr
  { 374,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #374 = LSR_f_rrs12
  { 375,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #375 = LSR_f_rru6
  { 376,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #376 = LSR_rrlimm
  { 377,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #377 = LSR_rrr
  { 378,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #378 = LSR_rrs12
  { 379,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #379 = LSR_rru6
  { 380,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #380 = MAX_f_rrlimm
  { 381,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #381 = MAX_f_rrr
  { 382,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #382 = MAX_f_rrs12
  { 383,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #383 = MAX_f_rru6
  { 384,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #384 = MAX_rrlimm
  { 385,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #385 = MAX_rrr
  { 386,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #386 = MAX_rrs12
  { 387,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #387 = MAX_rru6
  { 388,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #388 = MIN_f_rrlimm
  { 389,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #389 = MIN_f_rrr
  { 390,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #390 = MIN_f_rrs12
  { 391,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #391 = MIN_f_rru6
  { 392,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #392 = MIN_rrlimm
  { 393,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #393 = MIN_rrr
  { 394,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #394 = MIN_rrs12
  { 395,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #395 = MIN_rru6
  { 396,	2,	1,	6,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #396 = MOV_S_NE_rlimm
  { 397,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #397 = MOV_S_NE_rr
  { 398,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #398 = MOV_S_rs3
  { 399,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #399 = MOV_S_s3
  { 400,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #400 = MOV_S_u8
  { 401,	2,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #401 = MOV_rlimm
  { 402,	2,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #402 = MOV_rr
  { 403,	2,	1,	4,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #403 = MOV_rs12
  { 404,	2,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #404 = MOV_ru6
  { 405,	5,	1,	4,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #405 = MOVcc
  { 406,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #406 = MPYMU_f_rrlimm
  { 407,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #407 = MPYMU_f_rrr
  { 408,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #408 = MPYMU_f_rrs12
  { 409,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #409 = MPYMU_f_rru6
  { 410,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #410 = MPYMU_rrlimm
  { 411,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #411 = MPYMU_rrr
  { 412,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #412 = MPYMU_rrs12
  { 413,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #413 = MPYMU_rru6
  { 414,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #414 = MPYM_f_rrlimm
  { 415,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #415 = MPYM_f_rrr
  { 416,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #416 = MPYM_f_rrs12
  { 417,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #417 = MPYM_f_rru6
  { 418,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #418 = MPYM_rrlimm
  { 419,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #419 = MPYM_rrr
  { 420,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #420 = MPYM_rrs12
  { 421,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #421 = MPYM_rru6
  { 422,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #422 = MPY_f_rrlimm
  { 423,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #423 = MPY_f_rrr
  { 424,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #424 = MPY_f_rrs12
  { 425,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #425 = MPY_f_rru6
  { 426,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #426 = MPY_rrlimm
  { 427,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #427 = MPY_rrr
  { 428,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #428 = MPY_rrs12
  { 429,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #429 = MPY_rru6
  { 430,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #430 = OR_f_rrlimm
  { 431,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #431 = OR_f_rrr
  { 432,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #432 = OR_f_rrs12
  { 433,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #433 = OR_f_rru6
  { 434,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #434 = OR_rrlimm
  { 435,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #435 = OR_rrr
  { 436,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #436 = OR_rrs12
  { 437,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #437 = OR_rru6
  { 438,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #438 = PCL_LD
  { 439,	0,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, nullptr, -1 ,nullptr },  // Inst #439 = POP_S_BLINK
  { 440,	1,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #440 = POP_S_r
  { 441,	0,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #441 = PUSH_S_BLINK
  { 442,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #442 = PUSH_S_r
  { 443,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #443 = ROR_f_rrlimm
  { 444,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #444 = ROR_f_rrr
  { 445,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #445 = ROR_f_rrs12
  { 446,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #446 = ROR_f_rru6
  { 447,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #447 = ROR_rrlimm
  { 448,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #448 = ROR_rrr
  { 449,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #449 = ROR_rrs12
  { 450,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #450 = ROR_rru6
  { 451,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #451 = SETEQ_f_rrlimm
  { 452,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #452 = SETEQ_f_rrr
  { 453,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #453 = SETEQ_f_rrs12
  { 454,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #454 = SETEQ_f_rru6
  { 455,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #455 = SETEQ_rrlimm
  { 456,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #456 = SETEQ_rrr
  { 457,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #457 = SETEQ_rrs12
  { 458,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #458 = SETEQ_rru6
  { 459,	2,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo42, -1 ,nullptr },  // Inst #459 = SEXB_f_rr
  { 460,	2,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #460 = SEXB_rr
  { 461,	2,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo42, -1 ,nullptr },  // Inst #461 = SEXH_f_rr
  { 462,	2,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #462 = SEXH_rr
  { 463,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #463 = SP_ADD_S
  { 464,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #464 = SP_ADD_SP_S
  { 465,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #465 = SP_LDB_S
  { 466,	2,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #466 = SP_LD_S
  { 467,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #467 = SP_STB_S
  { 468,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #468 = SP_ST_S
  { 469,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #469 = SP_SUB_SP_S
  { 470,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #470 = STB_AB_rs9
  { 471,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #471 = STB_AW_rs9
  { 472,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #472 = STB_DI_AB_rs9
  { 473,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #473 = STB_DI_AW_rs9
  { 474,	3,	0,	8,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #474 = STB_DI_limm
  { 475,	3,	0,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #475 = STB_DI_rs9
  { 476,	3,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #476 = STB_S_OFF
  { 477,	3,	0,	8,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #477 = STB_limm
  { 478,	3,	0,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #478 = STB_rs9
  { 479,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #479 = STH_AB_rs9
  { 480,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #480 = STH_AW_rs9
  { 481,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #481 = STH_DI_AB_rs9
  { 482,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #482 = STH_DI_AW_rs9
  { 483,	3,	0,	8,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #483 = STH_DI_limm
  { 484,	3,	0,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #484 = STH_DI_rs9
  { 485,	3,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #485 = STH_S_OFF
  { 486,	3,	0,	8,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #486 = STH_limm
  { 487,	3,	0,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #487 = STH_rs9
  { 488,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #488 = ST_AB_rs9
  { 489,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #489 = ST_AW_rs9
  { 490,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #490 = ST_DI_AB_rs9
  { 491,	4,	1,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #491 = ST_DI_AW_rs9
  { 492,	3,	0,	8,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #492 = ST_DI_limm
  { 493,	3,	0,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #493 = ST_DI_rs9
  { 494,	3,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #494 = ST_S_OFF
  { 495,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #495 = ST_S_s11
  { 496,	3,	0,	8,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #496 = ST_limm
  { 497,	3,	0,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #497 = ST_rs9
  { 498,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #498 = SUB1_f_rrlimm
  { 499,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #499 = SUB1_f_rrr
  { 500,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #500 = SUB1_f_rrs12
  { 501,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #501 = SUB1_f_rru6
  { 502,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #502 = SUB1_rrlimm
  { 503,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #503 = SUB1_rrr
  { 504,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #504 = SUB1_rrs12
  { 505,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #505 = SUB1_rru6
  { 506,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #506 = SUB2_f_rrlimm
  { 507,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #507 = SUB2_f_rrr
  { 508,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #508 = SUB2_f_rrs12
  { 509,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #509 = SUB2_f_rru6
  { 510,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #510 = SUB2_rrlimm
  { 511,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #511 = SUB2_rrr
  { 512,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #512 = SUB2_rrs12
  { 513,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #513 = SUB2_rru6
  { 514,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #514 = SUB3_f_rrlimm
  { 515,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #515 = SUB3_f_rrr
  { 516,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #516 = SUB3_f_rrs12
  { 517,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #517 = SUB3_f_rru6
  { 518,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #518 = SUB3_rrlimm
  { 519,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #519 = SUB3_rrr
  { 520,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #520 = SUB3_rrs12
  { 521,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #521 = SUB3_rru6
  { 522,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #522 = SUB_S_rrr
  { 523,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #523 = SUB_S_ru3
  { 524,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #524 = SUB_S_ru5
  { 525,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #525 = SUB_f_rrlimm
  { 526,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #526 = SUB_f_rrr
  { 527,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #527 = SUB_f_rrs12
  { 528,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #528 = SUB_f_rru6
  { 529,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #529 = SUB_rrlimm
  { 530,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #530 = SUB_rrr
  { 531,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #531 = SUB_rrs12
  { 532,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #532 = SUB_rru6
  { 533,	3,	1,	8,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr },  // Inst #533 = XOR_f_rrlimm
  { 534,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #534 = XOR_f_rrr
  { 535,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo47, -1 ,nullptr },  // Inst #535 = XOR_f_rrs12
  { 536,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #536 = XOR_f_rru6
  { 537,	3,	1,	8,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #537 = XOR_rrlimm
  { 538,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #538 = XOR_rrr
  { 539,	3,	1,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #539 = XOR_rrs12
  { 540,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #540 = XOR_rru6
};

extern const char ARCInstrNameData[] = {
  /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
  /* 9 */ 'L', 'D', '_', 'S', '_', 's', '1', '1', 0,
  /* 18 */ 'S', 'T', '_', 'S', '_', 's', '1', '1', 0,
  /* 27 */ 'M', 'O', 'V', '_', 'r', 's', '1', '2', 0,
  /* 36 */ 'S', 'U', 'B', '1', '_', 'r', 'r', 's', '1', '2', 0,
  /* 47 */ 'S', 'U', 'B', '2', '_', 'r', 'r', 's', '1', '2', 0,
  /* 58 */ 'S', 'U', 'B', '3', '_', 'r', 'r', 's', '1', '2', 0,
  /* 69 */ 'S', 'U', 'B', '_', 'r', 'r', 's', '1', '2', 0,
  /* 79 */ 'A', 'D', 'D', '_', 'r', 'r', 's', '1', '2', 0,
  /* 89 */ 'A', 'N', 'D', '_', 'r', 'r', 's', '1', '2', 0,
  /* 99 */ 'A', 'S', 'L', '_', 'r', 'r', 's', '1', '2', 0,
  /* 109 */ 'M', 'P', 'Y', 'M', '_', 'r', 'r', 's', '1', '2', 0,
  /* 120 */ 'M', 'I', 'N', '_', 'r', 'r', 's', '1', '2', 0,
  /* 130 */ 'S', 'E', 'T', 'E', 'Q', '_', 'r', 'r', 's', '1', '2', 0,
  /* 142 */ 'R', 'O', 'R', '_', 'r', 'r', 's', '1', '2', 0,
  /* 152 */ 'X', 'O', 'R', '_', 'r', 'r', 's', '1', '2', 0,
  /* 162 */ 'A', 'S', 'R', '_', 'r', 'r', 's', '1', '2', 0,
  /* 172 */ 'L', 'S', 'R', '_', 'r', 'r', 's', '1', '2', 0,
  /* 182 */ 'M', 'P', 'Y', 'M', 'U', '_', 'r', 'r', 's', '1', '2', 0,
  /* 194 */ 'M', 'A', 'X', '_', 'r', 'r', 's', '1', '2', 0,
  /* 204 */ 'M', 'P', 'Y', '_', 'r', 'r', 's', '1', '2', 0,
  /* 214 */ 'S', 'U', 'B', '1', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 227 */ 'S', 'U', 'B', '2', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 240 */ 'S', 'U', 'B', '3', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 253 */ 'S', 'U', 'B', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 265 */ 'A', 'D', 'D', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 277 */ 'A', 'N', 'D', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 289 */ 'A', 'S', 'L', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 301 */ 'M', 'P', 'Y', 'M', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 314 */ 'M', 'I', 'N', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 326 */ 'S', 'E', 'T', 'E', 'Q', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 340 */ 'R', 'O', 'R', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 352 */ 'X', 'O', 'R', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 364 */ 'A', 'S', 'R', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 376 */ 'L', 'S', 'R', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 388 */ 'M', 'P', 'Y', 'M', 'U', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 402 */ 'M', 'A', 'X', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 414 */ 'M', 'P', 'Y', '_', 'f', '_', 'r', 'r', 's', '1', '2', 0,
  /* 426 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
  /* 434 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
  /* 442 */ 'M', 'O', 'V', '_', 'S', '_', 's', '3', 0,
  /* 451 */ 'A', 'D', 'D', '_', 'S', '_', 'l', 'i', 'm', 'm', 's', '3', 0,
  /* 464 */ 'C', 'M', 'P', '_', 'S', '_', 'l', 'i', 'm', 'm', 's', '3', 0,
  /* 477 */ 'A', 'D', 'D', '_', 'S', '_', 'r', 's', '3', 0,
  /* 487 */ 'C', 'M', 'P', '_', 'S', '_', 'r', 's', '3', 0,
  /* 497 */ 'M', 'O', 'V', '_', 'S', '_', 'r', 's', '3', 0,
  /* 507 */ 'S', 'U', 'B', '_', 'S', '_', 'r', 'u', '3', 0,
  /* 517 */ 'A', 'D', 'D', '_', 'S', '_', 'r', 'u', '3', 0,
  /* 527 */ 'A', 'S', 'L', '_', 'S', '_', 'r', 'u', '3', 0,
  /* 537 */ 'A', 'S', 'R', '_', 'S', '_', 'r', 'u', '3', 0,
  /* 547 */ 'S', 'U', 'B', '_', 'S', '_', 'r', 'u', '5', 0,
  /* 557 */ 'B', 'M', 'S', 'K', '_', 'S', '_', 'r', 'u', '5', 0,
  /* 568 */ 'A', 'S', 'L', '_', 'S', '_', 'r', 'u', '5', 0,
  /* 578 */ 'B', 'C', 'L', 'R', '_', 'S', '_', 'r', 'u', '5', 0,
  /* 589 */ 'A', 'S', 'R', '_', 'S', '_', 'r', 'u', '5', 0,
  /* 599 */ 'L', 'S', 'R', '_', 'S', '_', 'r', 'u', '5', 0,
  /* 609 */ 'B', 'S', 'E', 'T', '_', 'S', '_', 'r', 'u', '5', 0,
  /* 620 */ 'B', 'T', 'S', 'T', '_', 'S', '_', 'r', 'u', '5', 0,
  /* 631 */ 'C', 'M', 'P', '_', 'r', 'u', '6', 0,
  /* 639 */ 'M', 'O', 'V', '_', 'r', 'u', '6', 0,
  /* 647 */ 'B', 'R', 'c', 'c', '_', 'r', 'u', '6', 0,
  /* 656 */ 'S', 'U', 'B', '1', '_', 'r', 'r', 'u', '6', 0,
  /* 666 */ 'S', 'U', 'B', '2', '_', 'r', 'r', 'u', '6', 0,
  /* 676 */ 'S', 'U', 'B', '3', '_', 'r', 'r', 'u', '6', 0,
  /* 686 */ 'S', 'U', 'B', '_', 'r', 'r', 'u', '6', 0,
  /* 695 */ 'A', 'D', 'D', '_', 'r', 'r', 'u', '6', 0,
  /* 704 */ 'A', 'N', 'D', '_', 'r', 'r', 'u', '6', 0,
  /* 713 */ 'A', 'S', 'L', '_', 'r', 'r', 'u', '6', 0,
  /* 722 */ 'M', 'P', 'Y', 'M', '_', 'r', 'r', 'u', '6', 0,
  /* 732 */ 'M', 'I', 'N', '_', 'r', 'r', 'u', '6', 0,
  /* 741 */ 'S', 'E', 'T', 'E', 'Q', '_', 'r', 'r', 'u', '6', 0,
  /* 752 */ 'R', 'O', 'R', '_', 'r', 'r', 'u', '6', 0,
  /* 761 */ 'X', 'O', 'R', '_', 'r', 'r', 'u', '6', 0,
  /* 770 */ 'A', 'S', 'R', '_', 'r', 'r', 'u', '6', 0,
  /* 779 */ 'L', 'S', 'R', '_', 'r', 'r', 'u', '6', 0,
  /* 788 */ 'A', 'D', 'D', '_', 'S', '_', 'r', 'r', 'u', '6', 0,
  /* 799 */ 'M', 'P', 'Y', 'M', 'U', '_', 'r', 'r', 'u', '6', 0,
  /* 810 */ 'M', 'A', 'X', '_', 'r', 'r', 'u', '6', 0,
  /* 819 */ 'M', 'P', 'Y', '_', 'r', 'r', 'u', '6', 0,
  /* 828 */ 'S', 'U', 'B', '1', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 840 */ 'S', 'U', 'B', '2', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 852 */ 'S', 'U', 'B', '3', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 864 */ 'S', 'U', 'B', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 875 */ 'A', 'D', 'D', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 886 */ 'A', 'N', 'D', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 897 */ 'A', 'S', 'L', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 908 */ 'M', 'P', 'Y', 'M', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 920 */ 'M', 'I', 'N', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 931 */ 'S', 'E', 'T', 'E', 'Q', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 944 */ 'R', 'O', 'R', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 955 */ 'X', 'O', 'R', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 966 */ 'A', 'S', 'R', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 977 */ 'L', 'S', 'R', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 988 */ 'M', 'P', 'Y', 'M', 'U', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 1001 */ 'M', 'A', 'X', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 1012 */ 'M', 'P', 'Y', '_', 'f', '_', 'r', 'r', 'u', '6', 0,
  /* 1023 */ 'A', 'D', 'D', '_', 'S', '_', 'u', '7', 0,
  /* 1032 */ 'L', 'D', 'I', '_', 'S', '_', 'u', '7', 0,
  /* 1041 */ 'C', 'M', 'P', '_', 'S', '_', 'u', '7', 0,
  /* 1050 */ 'M', 'O', 'V', '_', 'S', '_', 'u', '8', 0,
  /* 1059 */ 'L', 'D', 'B', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1070 */ 'S', 'T', 'B', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1081 */ 'L', 'D', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1091 */ 'L', 'D', 'H', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1102 */ 'S', 'T', 'H', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1113 */ 'L', 'D', 'B', '_', 'D', 'I', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1127 */ 'S', 'T', 'B', '_', 'D', 'I', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1141 */ 'L', 'D', '_', 'D', 'I', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1154 */ 'L', 'D', 'H', '_', 'D', 'I', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1168 */ 'S', 'T', 'H', '_', 'D', 'I', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1182 */ 'S', 'T', '_', 'D', 'I', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1195 */ 'L', 'D', 'B', '_', 'X', '_', 'D', 'I', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1211 */ 'L', 'D', 'H', '_', 'X', '_', 'D', 'I', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1227 */ 'S', 'T', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1237 */ 'L', 'D', 'B', '_', 'X', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1250 */ 'L', 'D', 'H', '_', 'X', '_', 'A', 'B', '_', 'r', 's', '9', 0,
  /* 1263 */ 'L', 'D', 'B', '_', 'r', 's', '9', 0,
  /* 1271 */ 'S', 'T', 'B', '_', 'r', 's', '9', 0,
  /* 1279 */ 'L', 'D', '_', 'r', 's', '9', 0,
  /* 1286 */ 'L', 'D', 'H', '_', 'r', 's', '9', 0,
  /* 1294 */ 'S', 'T', 'H', '_', 'r', 's', '9', 0,
  /* 1302 */ 'L', 'D', 'B', '_', 'D', 'I', '_', 'r', 's', '9', 0,
  /* 1313 */ 'S', 'T', 'B', '_', 'D', 'I', '_', 'r', 's', '9', 0,
  /* 1324 */ 'L', 'D', '_', 'D', 'I', '_', 'r', 's', '9', 0,
  /* 1334 */ 'L', 'D', 'H', '_', 'D', 'I', '_', 'r', 's', '9', 0,
  /* 1345 */ 'S', 'T', 'H', '_', 'D', 'I', '_', 'r', 's', '9', 0,
  /* 1356 */ 'S', 'T', '_', 'D', 'I', '_', 'r', 's', '9', 0,
  /* 1366 */ 'L', 'D', 'B', '_', 'X', '_', 'D', 'I', '_', 'r', 's', '9', 0,
  /* 1379 */ 'L', 'D', 'H', '_', 'X', '_', 'D', 'I', '_', 'r', 's', '9', 0,
  /* 1392 */ 'S', 'T', '_', 'r', 's', '9', 0,
  /* 1399 */ 'L', 'D', 'B', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1410 */ 'S', 'T', 'B', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1421 */ 'L', 'D', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1431 */ 'L', 'D', 'H', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1442 */ 'S', 'T', 'H', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1453 */ 'L', 'D', 'B', '_', 'D', 'I', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1467 */ 'S', 'T', 'B', '_', 'D', 'I', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1481 */ 'L', 'D', '_', 'D', 'I', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1494 */ 'L', 'D', 'H', '_', 'D', 'I', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1508 */ 'S', 'T', 'H', '_', 'D', 'I', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1522 */ 'S', 'T', '_', 'D', 'I', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1535 */ 'L', 'D', 'B', '_', 'X', '_', 'D', 'I', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1551 */ 'L', 'D', 'H', '_', 'X', '_', 'D', 'I', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1567 */ 'S', 'T', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1577 */ 'L', 'D', 'B', '_', 'X', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1590 */ 'L', 'D', 'H', '_', 'X', '_', 'A', 'W', '_', 'r', 's', '9', 0,
  /* 1603 */ 'L', 'D', 'B', '_', 'X', '_', 'r', 's', '9', 0,
  /* 1613 */ 'L', 'D', 'H', '_', 'X', '_', 'r', 's', '9', 0,
  /* 1623 */ 'G', '_', 'F', 'M', 'A', 0,
  /* 1629 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
  /* 1636 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'S', 'U', 'B', 0,
  /* 1653 */ 'G', '_', 'S', 'U', 'B', 0,
  /* 1659 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
  /* 1675 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
  /* 1687 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
  /* 1697 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
  /* 1715 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
  /* 1723 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0,
  /* 1744 */ 'G', '_', 'D', 'Y', 'N', '_', 'S', 'T', 'A', 'C', 'K', 'A', 'L', 'L', 'O', 'C', 0,
  /* 1761 */ 'G', '_', 'F', 'M', 'A', 'D', 0,
  /* 1768 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 1787 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 1798 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 1817 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 1828 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'L', 'O', 'A', 'D', 0,
  /* 1843 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
  /* 1850 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
  /* 1857 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'A', 'D', 'D', 0,
  /* 1874 */ 'G', '_', 'A', 'D', 'D', 0,
  /* 1880 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
  /* 1896 */ 'P', 'C', 'L', '_', 'L', 'D', 0,
  /* 1903 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
  /* 1920 */ 'G', '_', 'A', 'N', 'D', 0,
  /* 1926 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
  /* 1942 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
  /* 1955 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
  /* 1964 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
  /* 1982 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
  /* 1999 */ 'G', 'E', 'N', '_', 'J', '_', 'S', '_', 'D', 0,
  /* 2009 */ 'G', 'E', 'N', '_', 'J', 'L', '_', 'S', '_', 'D', 0,
  /* 2020 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
  /* 2028 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
  /* 2036 */ 'G', '_', 'F', 'E', 'N', 'C', 'E', 0,
  /* 2044 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
  /* 2057 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
  /* 2065 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
  /* 2073 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0,
  /* 2088 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0,
  /* 2103 */ 'G', '_', 'J', 'U', 'M', 'P', '_', 'T', 'A', 'B', 'L', 'E', 0,
  /* 2116 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
  /* 2123 */ 'G', 'E', 'N', '_', 'S', 'U', 'B', '_', 'S', '_', 'N', 'E', 0,
  /* 2136 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
  /* 2149 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'T', 'O', 'R', 'E', 0,
  /* 2165 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
  /* 2173 */ 'G', '_', 'B', 'I', 'T', 'R', 'E', 'V', 'E', 'R', 'S', 'E', 0,
  /* 2186 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
  /* 2196 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
  /* 2211 */ 'G', '_', 'F', 'C', 'A', 'N', 'O', 'N', 'I', 'C', 'A', 'L', 'I', 'Z', 'E', 0,
  /* 2227 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
  /* 2245 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
  /* 2263 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
  /* 2278 */ 'L', 'D', 'B', '_', 'S', '_', 'O', 'F', 'F', 0,
  /* 2288 */ 'S', 'T', 'B', '_', 'S', '_', 'O', 'F', 'F', 0,
  /* 2298 */ 'L', 'D', '_', 'S', '_', 'O', 'F', 'F', 0,
  /* 2307 */ 'L', 'D', 'H', '_', 'S', '_', 'O', 'F', 'F', 0,
  /* 2317 */ 'S', 'T', 'H', '_', 'S', '_', 'O', 'F', 'F', 0,
  /* 2327 */ 'S', 'T', '_', 'S', '_', 'O', 'F', 'F', 0,
  /* 2336 */ 'L', 'D', 'H', '_', 'S', '_', 'X', '_', 'O', 'F', 'F', 0,
  /* 2348 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
  /* 2355 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
  /* 2370 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
  /* 2384 */ 'G', '_', 'S', 'E', 'X', 'T', '_', 'I', 'N', 'R', 'E', 'G', 0,
  /* 2397 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
  /* 2411 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
  /* 2428 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
  /* 2445 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
  /* 2452 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
  /* 2460 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
  /* 2468 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
  /* 2476 */ 'G', 'E', 'T', 'F', 'I', 0,
  /* 2482 */ 'G', '_', 'P', 'H', 'I', 0,
  /* 2488 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
  /* 2497 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
  /* 2506 */ 'J', 0,
  /* 2508 */ 'G', 'E', 'N', '_', 'J', '_', 'S', '_', 'D', '_', 'B', 'L', 'I', 'N', 'K', 0,
  /* 2524 */ 'P', 'U', 'S', 'H', '_', 'S', '_', 'B', 'L', 'I', 'N', 'K', 0,
  /* 2537 */ 'J', '_', 'S', '_', 'B', 'L', 'I', 'N', 'K', 0,
  /* 2547 */ 'P', 'O', 'P', '_', 'S', '_', 'B', 'L', 'I', 'N', 'K', 0,
  /* 2559 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
  /* 2570 */ 'B', 'L', 0,
  /* 2573 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 2582 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 2592 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 2601 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 2618 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
  /* 2638 */ 'G', '_', 'S', 'H', 'L', 0,
  /* 2644 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0,
  /* 2652 */ 'J', 'L', 0,
  /* 2655 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
  /* 2675 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
  /* 2702 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
  /* 2723 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
  /* 2735 */ 'K', 'I', 'L', 'L', 0,
  /* 2740 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
  /* 2747 */ 'G', '_', 'M', 'U', 'L', 0,
  /* 2753 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
  /* 2760 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
  /* 2767 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
  /* 2774 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
  /* 2784 */ 'G', '_', 'F', 'M', 'I', 'N', 'I', 'M', 'U', 'M', 0,
  /* 2795 */ 'G', '_', 'F', 'M', 'A', 'X', 'I', 'M', 'U', 'M', 0,
  /* 2806 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', 0,
  /* 2816 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', 0,
  /* 2826 */ 'G', '_', 'F', 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', 0,
  /* 2838 */ 'G', '_', 'S', 'M', 'I', 'N', 0,
  /* 2845 */ 'G', '_', 'U', 'M', 'I', 'N', 0,
  /* 2852 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
  /* 2869 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
  /* 2885 */ 'G', '_', 'F', 'S', 'I', 'N', 0,
  /* 2892 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
  /* 2908 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
  /* 2925 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
  /* 2933 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
  /* 2941 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
  /* 2949 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
  /* 2957 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
  /* 2965 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
  /* 2973 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
  /* 2982 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
  /* 2990 */ 'G', '_', 'G', 'E', 'P', 0,
  /* 2996 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
  /* 3005 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
  /* 3014 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
  /* 3021 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
  /* 3028 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
  /* 3036 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
  /* 3049 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
  /* 3061 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
  /* 3076 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
  /* 3083 */ 'S', 'T', 'B', '_', 'F', 'A', 'R', 0,
  /* 3091 */ 'S', 'T', 'H', '_', 'F', 'A', 'R', 0,
  /* 3099 */ 'S', 'T', '_', 'F', 'A', 'R', 0,
  /* 3106 */ 'G', '_', 'B', 'R', 0,
  /* 3111 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', '_', 'B', 'R', 0,
  /* 3124 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
  /* 3137 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
  /* 3162 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
  /* 3169 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
  /* 3176 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0,
  /* 3185 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
  /* 3200 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
  /* 3217 */ 'G', '_', 'X', 'O', 'R', 0,
  /* 3223 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
  /* 3239 */ 'G', '_', 'O', 'R', 0,
  /* 3244 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
  /* 3259 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
  /* 3270 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
  /* 3277 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
  /* 3294 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
  /* 3309 */ 'G', '_', 'F', 'C', 'O', 'S', 0,
  /* 3316 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0,
  /* 3333 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
  /* 3350 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
  /* 3380 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
  /* 3407 */ 'G', 'E', 'N', '_', 'A', 'D', 'D', '1', '_', 'S', 0,
  /* 3418 */ 'G', 'E', 'N', '_', 'A', 'D', 'D', '2', '_', 'S', 0,
  /* 3429 */ 'G', 'E', 'N', '_', 'A', 'D', 'D', '3', '_', 'S', 0,
  /* 3440 */ 'G', 'P', '_', 'L', 'D', 'B', '_', 'S', 0,
  /* 3449 */ 'S', 'P', '_', 'L', 'D', 'B', '_', 'S', 0,
  /* 3458 */ 'S', 'P', '_', 'S', 'T', 'B', '_', 'S', 0,
  /* 3467 */ 'G', 'E', 'N', '_', 'E', 'X', 'T', 'B', '_', 'S', 0,
  /* 3478 */ 'G', 'E', 'N', '_', 'S', 'U', 'B', '_', 'S', 0,
  /* 3488 */ 'G', 'E', 'N', '_', 'S', 'E', 'X', 'B', '_', 'S', 0,
  /* 3499 */ 'G', 'E', 'N', '_', 'B', 'I', 'C', '_', 'S', 0,
  /* 3509 */ 'G', 'P', '_', 'A', 'D', 'D', '_', 'S', 0,
  /* 3518 */ 'S', 'P', '_', 'A', 'D', 'D', '_', 'S', 0,
  /* 3527 */ 'G', 'P', '_', 'L', 'D', '_', 'S', 0,
  /* 3535 */ 'S', 'P', '_', 'L', 'D', '_', 'S', 0,
  /* 3543 */ 'C', 'O', 'M', 'P', 'A', 'C', 'T', '_', 'L', 'D', '_', 'S', 0,
  /* 3556 */ 'G', 'E', 'N', '_', 'A', 'N', 'D', '_', 'S', 0,
  /* 3566 */ 'B', 'G', 'E', '_', 'S', 0,
  /* 3572 */ 'B', 'L', 'E', '_', 'S', 0,
  /* 3578 */ 'B', 'N', 'E', '_', 'S', 0,
  /* 3584 */ 'G', 'E', 'N', '_', 'J', 'N', 'E', '_', 'S', 0,
  /* 3594 */ 'B', 'R', 'N', 'E', '_', 'S', 0,
  /* 3601 */ 'L', 'E', 'A', 'V', 'E', '_', 'S', 0,
  /* 3609 */ 'G', 'E', 'N', '_', 'N', 'E', 'G', '_', 'S', 0,
  /* 3619 */ 'G', 'P', '_', 'L', 'D', 'H', '_', 'S', 0,
  /* 3628 */ 'G', 'E', 'N', '_', 'E', 'X', 'T', 'H', '_', 'S', 0,
  /* 3639 */ 'G', 'E', 'N', '_', 'S', 'E', 'X', 'H', '_', 'S', 0,
  /* 3650 */ 'E', 'I', '_', 'S', 0,
  /* 3655 */ 'B', 'H', 'I', '_', 'S', 0,
  /* 3661 */ 'J', 'L', 'I', '_', 'S', 0,
  /* 3667 */ 'G', 'E', 'N', '_', 'S', 'W', 'I', '_', 'S', 0,
  /* 3677 */ 'G', 'E', 'N', '_', 'J', '_', 'S', 0,
  /* 3685 */ 'G', 'E', 'N', '_', 'B', 'R', 'K', '_', 'S', 0,
  /* 3695 */ 'G', 'E', 'N', '_', 'A', 'S', '1', 'L', '_', 'S', 0,
  /* 3706 */ 'B', 'L', '_', 'S', 0,
  /* 3711 */ 'G', 'E', 'N', '_', 'J', 'L', '_', 'S', 0,
  /* 3720 */ 'G', 'E', 'N', '_', 'A', 'S', 'L', '_', 'S', 0,
  /* 3730 */ 'B', 'L', 'O', '_', 'S', 0,
  /* 3736 */ 'G', 'E', 'N', '_', 'T', 'R', 'A', 'P', '_', 'S', 0,
  /* 3747 */ 'G', 'E', 'N', '_', 'U', 'N', 'I', 'M', 'P', '_', 'S', 0,
  /* 3759 */ 'G', 'E', 'N', '_', 'N', 'O', 'P', '_', 'S', 0,
  /* 3769 */ 'S', 'P', '_', 'S', 'U', 'B', '_', 'S', 'P', '_', 'S', 0,
  /* 3781 */ 'S', 'P', '_', 'A', 'D', 'D', '_', 'S', 'P', '_', 'S', 0,
  /* 3793 */ 'B', 'E', 'Q', '_', 'S', 0,
  /* 3799 */ 'G', 'E', 'N', '_', 'J', 'E', 'Q', '_', 'S', 0,
  /* 3809 */ 'B', 'R', 'E', 'Q', '_', 'S', 0,
  /* 3816 */ 'G', 'E', 'N', '_', 'A', 'S', '1', 'R', '_', 'S', 0,
  /* 3827 */ 'G', 'E', 'N', '_', 'L', 'S', '1', 'R', '_', 'S', 0,
  /* 3838 */ 'E', 'N', 'T', 'E', 'R', '_', 'S', 0,
  /* 3846 */ 'G', 'E', 'N', '_', 'X', 'O', 'R', '_', 'S', 0,
  /* 3856 */ 'G', 'E', 'N', '_', 'O', 'R', '_', 'S', 0,
  /* 3865 */ 'G', 'E', 'N', '_', 'A', 'S', 'R', '_', 'S', 0,
  /* 3875 */ 'G', 'E', 'N', '_', 'L', 'S', 'R', '_', 'S', 0,
  /* 3885 */ 'G', 'E', 'N', '_', 'A', 'B', 'S', '_', 'S', 0,
  /* 3895 */ 'B', 'H', 'S', '_', 'S', 0,
  /* 3901 */ 'B', 'L', 'S', '_', 'S', 0,
  /* 3907 */ 'B', 'G', 'T', '_', 'S', 0,
  /* 3913 */ 'B', 'L', 'T', '_', 'S', 0,
  /* 3919 */ 'G', 'E', 'N', '_', 'N', 'O', 'T', '_', 'S', 0,
  /* 3929 */ 'G', 'E', 'N', '_', 'T', 'S', 'T', '_', 'S', 0,
  /* 3939 */ 'S', 'P', '_', 'S', 'T', '_', 'S', 0,
  /* 3947 */ 'G', 'E', 'N', '_', 'M', 'P', 'Y', 'U', 'W', '_', 'S', 0,
  /* 3959 */ 'G', 'E', 'N', '_', 'M', 'P', 'Y', 'W', '_', 'S', 0,
  /* 3970 */ 'G', 'E', 'N', '_', 'M', 'P', 'Y', '_', 'S', 0,
  /* 3980 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
  /* 3990 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
  /* 3999 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
  /* 4012 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
  /* 4026 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
  /* 4050 */ 'G', '_', 'B', 'R', 'J', 'T', 0,
  /* 4057 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
  /* 4078 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
  /* 4098 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
  /* 4110 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
  /* 4121 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
  /* 4132 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
  /* 4143 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
  /* 4154 */ 'G', '_', 'F', 'R', 'I', 'N', 'T', 0,
  /* 4162 */ 'G', '_', 'F', 'N', 'E', 'A', 'R', 'B', 'Y', 'I', 'N', 'T', 0,
  /* 4175 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
  /* 4185 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
  /* 4200 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
  /* 4209 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0,
  /* 4217 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
  /* 4227 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
  /* 4244 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
  /* 4252 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
  /* 4259 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
  /* 4268 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
  /* 4275 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
  /* 4282 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
  /* 4289 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
  /* 4296 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
  /* 4303 */ 'G', '_', 'S', 'M', 'A', 'X', 0,
  /* 4310 */ 'G', '_', 'U', 'M', 'A', 'X', 0,
  /* 4317 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
  /* 4334 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
  /* 4350 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
  /* 4364 */ 'C', 'O', 'P', 'Y', 0,
  /* 4369 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
  /* 4376 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
  /* 4383 */ 'B', 'c', 'c', 0,
  /* 4387 */ 'M', 'O', 'V', 'c', 'c', 0,
  /* 4393 */ 'C', 'O', 'M', 'P', 'A', 'C', 'T', '_', 'M', 'O', 'V', '_', 'S', '_', 'h', 'r', 'e', 'g', 0,
  /* 4412 */ 'J', '_', 'L', 'I', 'm', 'm', 0,
  /* 4419 */ 'J', 'L', '_', 'L', 'I', 'm', 'm', 0,
  /* 4427 */ 'L', 'D', 'B', '_', 'l', 'i', 'm', 'm', 0,
  /* 4436 */ 'S', 'T', 'B', '_', 'l', 'i', 'm', 'm', 0,
  /* 4445 */ 'L', 'D', '_', 'l', 'i', 'm', 'm', 0,
  /* 4453 */ 'L', 'D', 'H', '_', 'l', 'i', 'm', 'm', 0,
  /* 4462 */ 'S', 'T', 'H', '_', 'l', 'i', 'm', 'm', 0,
  /* 4471 */ 'L', 'D', 'B', '_', 'D', 'I', '_', 'l', 'i', 'm', 'm', 0,
  /* 4483 */ 'S', 'T', 'B', '_', 'D', 'I', '_', 'l', 'i', 'm', 'm', 0,
  /* 4495 */ 'L', 'D', '_', 'D', 'I', '_', 'l', 'i', 'm', 'm', 0,
  /* 4506 */ 'L', 'D', 'H', '_', 'D', 'I', '_', 'l', 'i', 'm', 'm', 0,
  /* 4518 */ 'S', 'T', 'H', '_', 'D', 'I', '_', 'l', 'i', 'm', 'm', 0,
  /* 4530 */ 'S', 'T', '_', 'D', 'I', '_', 'l', 'i', 'm', 'm', 0,
  /* 4541 */ 'L', 'D', 'B', '_', 'X', '_', 'D', 'I', '_', 'l', 'i', 'm', 'm', 0,
  /* 4555 */ 'L', 'D', 'H', '_', 'X', '_', 'D', 'I', '_', 'l', 'i', 'm', 'm', 0,
  /* 4569 */ 'C', 'O', 'M', 'P', 'A', 'C', 'T', '_', 'M', 'O', 'V', '_', 'S', '_', 'l', 'i', 'm', 'm', 0,
  /* 4588 */ 'S', 'T', '_', 'l', 'i', 'm', 'm', 0,
  /* 4596 */ 'L', 'D', 'B', '_', 'X', '_', 'l', 'i', 'm', 'm', 0,
  /* 4607 */ 'L', 'D', 'H', '_', 'X', '_', 'l', 'i', 'm', 'm', 0,
  /* 4618 */ 'L', 'D', 'B', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4628 */ 'L', 'D', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4637 */ 'M', 'O', 'V', '_', 'S', '_', 'N', 'E', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4652 */ 'L', 'D', 'H', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4662 */ 'L', 'D', 'B', '_', 'D', 'I', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4675 */ 'L', 'D', '_', 'D', 'I', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4687 */ 'L', 'D', 'H', '_', 'D', 'I', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4700 */ 'L', 'D', 'B', '_', 'X', '_', 'D', 'I', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4715 */ 'L', 'D', 'H', '_', 'X', '_', 'D', 'I', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4730 */ 'C', 'M', 'P', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4740 */ 'A', 'D', 'D', '_', 'S', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4752 */ 'C', 'M', 'P', '_', 'S', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4764 */ 'M', 'O', 'V', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4774 */ 'L', 'D', 'B', '_', 'X', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4786 */ 'L', 'D', 'H', '_', 'X', '_', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4798 */ 'S', 'U', 'B', '1', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4810 */ 'S', 'U', 'B', '2', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4822 */ 'S', 'U', 'B', '3', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4834 */ 'S', 'U', 'B', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4845 */ 'A', 'D', 'D', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4856 */ 'A', 'N', 'D', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4867 */ 'A', 'S', 'L', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4878 */ 'M', 'P', 'Y', 'M', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4890 */ 'M', 'I', 'N', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4901 */ 'S', 'E', 'T', 'E', 'Q', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4914 */ 'R', 'O', 'R', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4925 */ 'X', 'O', 'R', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4936 */ 'A', 'S', 'R', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4947 */ 'L', 'S', 'R', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4958 */ 'M', 'P', 'Y', 'M', 'U', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4971 */ 'M', 'A', 'X', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4982 */ 'M', 'P', 'Y', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 4993 */ 'S', 'U', 'B', '1', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5007 */ 'S', 'U', 'B', '2', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5021 */ 'S', 'U', 'B', '3', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5035 */ 'S', 'U', 'B', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5048 */ 'A', 'D', 'D', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5061 */ 'A', 'N', 'D', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5074 */ 'A', 'S', 'L', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5087 */ 'M', 'P', 'Y', 'M', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5101 */ 'M', 'I', 'N', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5114 */ 'S', 'E', 'T', 'E', 'Q', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5129 */ 'R', 'O', 'R', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5142 */ 'X', 'O', 'R', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5155 */ 'A', 'S', 'R', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5168 */ 'L', 'S', 'R', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5181 */ 'M', 'P', 'Y', 'M', 'U', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5196 */ 'M', 'A', 'X', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5209 */ 'M', 'P', 'Y', '_', 'f', '_', 'r', 'r', 'l', 'i', 'm', 'm', 0,
  /* 5222 */ 'B', 'R', 'c', 'c', '_', 'r', 'u', '6', '_', 'p', 0,
  /* 5233 */ 'B', 'R', 'c', 'c', '_', 'r', 'r', '_', 'p', 0,
  /* 5243 */ 'P', 'U', 'S', 'H', '_', 'S', '_', 'r', 0,
  /* 5252 */ 'P', 'O', 'P', '_', 'S', '_', 'r', 0,
  /* 5260 */ 'S', 'E', 'X', 'B', '_', 'r', 'r', 0,
  /* 5268 */ 'M', 'O', 'V', '_', 'S', '_', 'N', 'E', '_', 'r', 'r', 0,
  /* 5280 */ 'S', 'E', 'X', 'H', '_', 'r', 'r', 0,
  /* 5288 */ 'C', 'M', 'P', '_', 'r', 'r', 0,
  /* 5295 */ 'A', 'D', 'D', '_', 'S', '_', 'r', 'r', 0,
  /* 5304 */ 'C', 'M', 'P', '_', 'S', '_', 'r', 'r', 0,
  /* 5313 */ 'M', 'O', 'V', '_', 'r', 'r', 0,
  /* 5320 */ 'B', 'R', 'c', 'c', '_', 'r', 'r', 0,
  /* 5328 */ 'S', 'E', 'X', 'B', '_', 'f', '_', 'r', 'r', 0,
  /* 5338 */ 'S', 'E', 'X', 'H', '_', 'f', '_', 'r', 'r', 0,
  /* 5348 */ 'S', 'U', 'B', '1', '_', 'r', 'r', 'r', 0,
  /* 5357 */ 'S', 'U', 'B', '2', '_', 'r', 'r', 'r', 0,
  /* 5366 */ 'S', 'U', 'B', '3', '_', 'r', 'r', 'r', 0,
  /* 5375 */ 'S', 'U', 'B', '_', 'r', 'r', 'r', 0,
  /* 5383 */ 'A', 'D', 'D', '_', 'r', 'r', 'r', 0,
  /* 5391 */ 'A', 'N', 'D', '_', 'r', 'r', 'r', 0,
  /* 5399 */ 'A', 'S', 'L', '_', 'r', 'r', 'r', 0,
  /* 5407 */ 'M', 'P', 'Y', 'M', '_', 'r', 'r', 'r', 0,
  /* 5416 */ 'M', 'I', 'N', '_', 'r', 'r', 'r', 0,
  /* 5424 */ 'S', 'E', 'T', 'E', 'Q', '_', 'r', 'r', 'r', 0,
  /* 5434 */ 'R', 'O', 'R', '_', 'r', 'r', 'r', 0,
  /* 5442 */ 'X', 'O', 'R', '_', 'r', 'r', 'r', 0,
  /* 5450 */ 'A', 'S', 'R', '_', 'r', 'r', 'r', 0,
  /* 5458 */ 'L', 'S', 'R', '_', 'r', 'r', 'r', 0,
  /* 5466 */ 'L', 'D', '_', 'S', '_', 'A', 'S', '_', 'r', 'r', 'r', 0,
  /* 5478 */ 'L', 'D', 'B', '_', 'S', '_', 'r', 'r', 'r', 0,
  /* 5488 */ 'S', 'U', 'B', '_', 'S', '_', 'r', 'r', 'r', 0,
  /* 5498 */ 'A', 'D', 'D', '_', 'S', '_', 'r', 'r', 'r', 0,
  /* 5508 */ 'L', 'D', '_', 'S', '_', 'r', 'r', 'r', 0,
  /* 5517 */ 'L', 'D', 'H', '_', 'S', '_', 'r', 'r', 'r', 0,
  /* 5527 */ 'M', 'P', 'Y', 'M', 'U', '_', 'r', 'r', 'r', 0,
  /* 5537 */ 'M', 'A', 'X', '_', 'r', 'r', 'r', 0,
  /* 5545 */ 'M', 'P', 'Y', '_', 'r', 'r', 'r', 0,
  /* 5553 */ 'S', 'U', 'B', '1', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5564 */ 'S', 'U', 'B', '2', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5575 */ 'S', 'U', 'B', '3', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5586 */ 'S', 'U', 'B', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5596 */ 'A', 'D', 'D', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5606 */ 'A', 'N', 'D', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5616 */ 'A', 'S', 'L', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5626 */ 'M', 'P', 'Y', 'M', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5637 */ 'M', 'I', 'N', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5647 */ 'S', 'E', 'T', 'E', 'Q', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5659 */ 'R', 'O', 'R', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5669 */ 'X', 'O', 'R', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5679 */ 'A', 'S', 'R', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5689 */ 'L', 'S', 'R', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5699 */ 'M', 'P', 'Y', 'M', 'U', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5711 */ 'M', 'A', 'X', '_', 'f', '_', 'r', 'r', 'r', 0,
  /* 5721 */ 'M', 'P', 'Y', '_', 'f', '_', 'r', 'r', 'r', 0,
};

extern const unsigned ARCInstrNameIndices[] = {
    2484U, 2774U, 3111U, 2892U, 2592U, 2573U, 2601U, 2735U, 
    2355U, 2370U, 2265U, 2397U, 3333U, 2186U, 2582U, 2044U, 
    4364U, 2116U, 4185U, 1942U, 2973U, 2723U, 4132U, 1982U, 
    4121U, 2136U, 3049U, 3036U, 3137U, 4012U, 4026U, 2655U, 
    2702U, 2675U, 2618U, 1874U, 1653U, 2747U, 4282U, 4289U, 
    2760U, 2767U, 1920U, 3239U, 3217U, 2263U, 2482U, 4350U, 
    2196U, 3980U, 3277U, 4200U, 3294U, 3185U, 1723U, 3316U, 
    4143U, 3259U, 4217U, 1697U, 1964U, 1843U, 1787U, 1817U, 
    1828U, 1768U, 1798U, 2165U, 2149U, 3350U, 2411U, 2428U, 
    1880U, 1659U, 1926U, 1903U, 3244U, 3223U, 4334U, 2869U, 
    4317U, 2852U, 1857U, 1636U, 2036U, 1955U, 3999U, 1675U, 
    3380U, 4259U, 1715U, 4110U, 4098U, 4175U, 2452U, 4252U, 
    2384U, 4268U, 2638U, 3169U, 3162U, 3021U, 3014U, 3990U, 
    2949U, 2065U, 2933U, 2028U, 2941U, 2057U, 2925U, 2020U, 
    2965U, 2957U, 2468U, 2460U, 1850U, 1629U, 2740U, 1623U, 
    1761U, 4275U, 2753U, 4296U, 3076U, 434U, 2445U, 426U, 
    0U, 2348U, 4244U, 1687U, 2488U, 2497U, 2996U, 3005U, 
    3270U, 2826U, 2211U, 2806U, 2816U, 2073U, 2088U, 2784U, 
    2795U, 2990U, 2559U, 2838U, 4303U, 2845U, 4310U, 3106U, 
    4050U, 4078U, 4057U, 3200U, 4376U, 2245U, 4369U, 2227U, 
    3028U, 2982U, 2173U, 2644U, 3309U, 2885U, 4209U, 3176U, 
    4154U, 4162U, 4227U, 3124U, 2103U, 1744U, 2908U, 3061U, 
    5233U, 5222U, 2476U, 3083U, 3091U, 3099U, 451U, 4740U, 
    5295U, 5498U, 788U, 477U, 517U, 1023U, 5048U, 5596U, 
    265U, 875U, 4845U, 5383U, 79U, 695U, 5061U, 5606U, 
    277U, 886U, 4856U, 5391U, 89U, 704U, 527U, 568U, 
    5074U, 5616U, 289U, 897U, 4867U, 5399U, 99U, 713U, 
    537U, 589U, 5155U, 5679U, 364U, 966U, 4936U, 5450U, 
    162U, 770U, 578U, 3793U, 3566U, 3907U, 3655U, 3895U, 
    2570U, 3572U, 3730U, 3901U, 3913U, 3706U, 557U, 3578U, 
    3108U, 3809U, 3594U, 5320U, 647U, 609U, 620U, 3445U, 
    4383U, 464U, 4752U, 5304U, 487U, 1041U, 4730U, 5288U, 
    631U, 3543U, 4393U, 4569U, 3650U, 3838U, 3885U, 3407U, 
    3418U, 3429U, 3556U, 3695U, 3816U, 3720U, 3865U, 3499U, 
    3685U, 3467U, 3628U, 3799U, 3711U, 2009U, 3584U, 3677U, 
    1999U, 2508U, 3827U, 3875U, 3947U, 3959U, 3970U, 3609U, 
    3759U, 3919U, 3856U, 3488U, 3639U, 3478U, 2123U, 3667U, 
    3736U, 3929U, 3747U, 3846U, 3509U, 3440U, 3619U, 3527U, 
    2506U, 2652U, 3661U, 4419U, 4412U, 2537U, 1059U, 1399U, 
    1113U, 1453U, 4471U, 4662U, 1302U, 2278U, 5478U, 1237U, 
    1577U, 1195U, 1535U, 4541U, 4700U, 1366U, 4596U, 4774U, 
    1603U, 4427U, 4618U, 1263U, 1091U, 1431U, 1154U, 1494U, 
    4506U, 4687U, 1334U, 2307U, 2336U, 5517U, 1250U, 1590U, 
    1211U, 1551U, 4555U, 4715U, 1379U, 4607U, 4786U, 1613U, 
    4453U, 4652U, 1286U, 1032U, 1081U, 1421U, 1141U, 1481U, 
    4495U, 4675U, 1324U, 5466U, 2298U, 5508U, 9U, 4445U, 
    4628U, 1279U, 3601U, 599U, 5168U, 5689U, 376U, 977U, 
    4947U, 5458U, 172U, 779U, 5196U, 5711U, 402U, 1001U, 
    4971U, 5537U, 194U, 810U, 5101U, 5637U, 314U, 920U, 
    4890U, 5416U, 120U, 732U, 4637U, 5268U, 497U, 442U, 
    1050U, 4764U, 5313U, 27U, 639U, 4387U, 5181U, 5699U, 
    388U, 988U, 4958U, 5527U, 182U, 799U, 5087U, 5626U, 
    301U, 908U, 4878U, 5407U, 109U, 722U, 5209U, 5721U, 
    414U, 1012U, 4982U, 5545U, 204U, 819U, 5130U, 5660U, 
    341U, 945U, 4915U, 5435U, 143U, 753U, 1896U, 2547U, 
    5252U, 2524U, 5243U, 5129U, 5659U, 340U, 944U, 4914U, 
    5434U, 142U, 752U, 5114U, 5647U, 326U, 931U, 4901U, 
    5424U, 130U, 741U, 5328U, 5260U, 5338U, 5280U, 3518U, 
    3781U, 3449U, 3535U, 3458U, 3939U, 3769U, 1070U, 1410U, 
    1127U, 1467U, 4483U, 1313U, 2288U, 4436U, 1271U, 1102U, 
    1442U, 1168U, 1508U, 4518U, 1345U, 2317U, 4462U, 1294U, 
    1227U, 1567U, 1182U, 1522U, 4530U, 1356U, 2327U, 18U, 
    4588U, 1392U, 4993U, 5553U, 214U, 828U, 4798U, 5348U, 
    36U, 656U, 5007U, 5564U, 227U, 840U, 4810U, 5357U, 
    47U, 666U, 5021U, 5575U, 240U, 852U, 4822U, 5366U, 
    58U, 676U, 5488U, 507U, 547U, 5035U, 5586U, 253U, 
    864U, 4834U, 5375U, 69U, 686U, 5142U, 5669U, 352U, 
    955U, 4925U, 5442U, 152U, 761U, 
};

static inline void InitARCMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(ARCInsts, ARCInstrNameIndices, ARCInstrNameData, 541);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct ARCGenInstrInfo : public TargetInstrInfo {
  explicit ARCGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
  ~ARCGenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const MCInstrDesc ARCInsts[];
extern const unsigned ARCInstrNameIndices[];
extern const char ARCInstrNameData[];
ARCGenInstrInfo::ARCGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(ARCInsts, ARCInstrNameIndices, ARCInstrNameData, 541);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace ARC {
namespace OpName {
enum {
OPERAND_LAST
};
} // end namespace OpName
} // end namespace ARC
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace ARC {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace ARC
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace ARC {
namespace OpTypes {
enum OperandType {
  GPR32Reduced = 0,
  MEMii = 1,
  MEMrlimm = 2,
  MEMrs9 = 3,
  brccond = 15,
  btarget = 16,
  btargetS10 = 17,
  btargetS13 = 18,
  btargetS21 = 19,
  btargetS25 = 20,
  btargetS7 = 21,
  btargetS8 = 22,
  btargetS9 = 23,
  calltargetS25 = 24,
  ccond = 25,
  cmovpred = 26,
  f32imm = 27,
  f64imm = 28,
  i16imm = 29,
  i1imm = 30,
  i32imm = 31,
  i64imm = 32,
  i8imm = 33,
  immU6 = 34,
  ptype0 = 35,
  ptype1 = 36,
  ptype2 = 37,
  ptype3 = 38,
  ptype4 = 39,
  ptype5 = 40,
  type0 = 41,
  type1 = 42,
  type2 = 43,
  type3 = 44,
  type4 = 45,
  type5 = 46,
  untyped_imm_0 = 47,
  GPR32 = 48,
  GPR_S = 49,
  SREG = 50,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace ARC
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace ARC {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  const int Offsets[] = {
    0,
    1,
    1,
    1,
    2,
    3,
    4,
    5,
    5,
    8,
    12,
    13,
    17,
    20,
    20,
    21,
    23,
    25,
    25,
    26,
    27,
    29,
    29,
    35,
    36,
    36,
    38,
    39,
    39,
    39,
    39,
    39,
    39,
    41,
    44,
    44,
    47,
    50,
    53,
    56,
    59,
    62,
    65,
    68,
    71,
    74,
    75,
    76,
    78,
    80,
    83,
    85,
    89,
    91,
    93,
    95,
    97,
    99,
    101,
    103,
    105,
    107,
    109,
    111,
    113,
    118,
    123,
    128,
    130,
    135,
    140,
    144,
    147,
    150,
    153,
    156,
    159,
    162,
    165,
    168,
    171,
    174,
    177,
    180,
    183,
    185,
    187,
    188,
    189,
    190,
    192,
    194,
    196,
    198,
    199,
    202,
    204,
    207,
    209,
    212,
    215,
    218,
    222,
    226,
    230,
    234,
    239,
    243,
    248,
    252,
    257,
    261,
    266,
    270,
    274,
    277,
    280,
    283,
    286,
    289,
    293,
    297,
    300,
    303,
    306,
    308,
    310,
    312,
    314,
    316,
    318,
    320,
    322,
    324,
    326,
    328,
    330,
    332,
    335,
    337,
    340,
    343,
    346,
    349,
    352,
    355,
    358,
    361,
    364,
    367,
    370,
    373,
    374,
    377,
    381,
    384,
    388,
    390,
    392,
    394,
    396,
    398,
    400,
    402,
    404,
    406,
    408,
    410,
    412,
    414,
    416,
    418,
    420,
    422,
    425,
    427,
    429,
    433,
    437,
    440,
    443,
    446,
    449,
    451,
    453,
    455,
    458,
    461,
    463,
    466,
    468,
    471,
    474,
    477,
    480,
    483,
    486,
    489,
    492,
    495,
    498,
    501,
    504,
    507,
    510,
    513,
    516,
    519,
    521,
    524,
    527,
    530,
    533,
    536,
    539,
    542,
    545,
    548,
    550,
    553,
    556,
    559,
    562,
    565,
    568,
    571,
    574,
    576,
    577,
    578,
    579,
    580,
    581,
    582,
    583,
    584,
    585,
    586,
    587,
    589,
    590,
    591,
    593,
    595,
    599,
    603,
    605,
    607,
    608,
    610,
    612,
    614,
    616,
    618,
    620,
    622,
    624,
    626,
    629,
    631,
    633,
    634,
    635,
    637,
    639,
    641,
    643,
    645,
    647,
    649,
    651,
    653,
    655,
    655,
    657,
    659,
    659,
    660,
    661,
    661,
    662,
    663,
    663,
    665,
    667,
    669,
    671,
    673,
    675,
    675,
    677,
    679,
    681,
    683,
    685,
    686,
    686,
    687,
    689,
    689,
    691,
    692,
    693,
    694,
    695,
    696,
    697,
    698,
    699,
    700,
    700,
    704,
    708,
    712,
    716,
    719,
    722,
    725,
    728,
    731,
    735,
    739,
    743,
    747,
    750,
    753,
    756,
    759,
    762,
    765,
    768,
    771,
    774,
    778,
    782,
    786,
    790,
    793,
    796,
    799,
    802,
    805,
    808,
    812,
    816,
    820,
    824,
    827,
    830,
    833,
    836,
    839,
    842,
    845,
    848,
    851,
    853,
    857,
    861,
    865,
    869,
    872,
    875,
    878,
    881,
    884,
    887,
    888,
    891,
    894,
    897,
    898,
    900,
    903,
    906,
    909,
    912,
    915,
    918,
    921,
    924,
    927,
    930,
    933,
    936,
    939,
    942,
    945,
    948,
    951,
    954,
    957,
    960,
    963,
    966,
    969,
    972,
    974,
    976,
    978,
    979,
    981,
    983,
    985,
    987,
    989,
    994,
    997,
    1000,
    1003,
    1006,
    1009,
    1012,
    1015,
    1018,
    1021,
    1024,
    1027,
    1030,
    1033,
    1036,
    1039,
    1042,
    1045,
    1048,
    1051,
    1054,
    1057,
    1060,
    1063,
    1066,
    1069,
    1072,
    1075,
    1078,
    1081,
    1084,
    1087,
    1090,
    1092,
    1092,
    1093,
    1093,
    1094,
    1097,
    1100,
    1103,
    1106,
    1109,
    1112,
    1115,
    1118,
    1121,
    1124,
    1127,
    1130,
    1133,
    1136,
    1139,
    1142,
    1144,
    1146,
    1148,
    1150,
    1152,
    1153,
    1155,
    1157,
    1159,
    1161,
    1162,
    1166,
    1170,
    1174,
    1178,
    1181,
    1184,
    1187,
    1190,
    1193,
    1197,
    1201,
    1205,
    1209,
    1212,
    1215,
    1218,
    1221,
    1224,
    1228,
    1232,
    1236,
    1240,
    1243,
    1246,
    1249,
    1250,
    1253,
    1256,
    1259,
    1262,
    1265,
    1268,
    1271,
    1274,
    1277,
    1280,
    1283,
    1286,
    1289,
    1292,
    1295,
    1298,
    1301,
    1304,
    1307,
    1310,
    1313,
    1316,
    1319,
    1322,
    1325,
    1328,
    1331,
    1334,
    1336,
    1339,
    1342,
    1345,
    1348,
    1351,
    1354,
    1357,
    1360,
    1363,
    1366,
    1369,
    1372,
    1375,
    1378,
    1381,
  };
  const int OpcodeOperandTypes[] = {
    -1, 
    /**/
    /**/
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    /**/
    -1, -1, OpTypes::i32imm, 
    -1, -1, -1, OpTypes::i32imm, 
    -1, 
    -1, -1, -1, OpTypes::i32imm, 
    -1, -1, OpTypes::i32imm, 
    /**/
    -1, 
    -1, -1, 
    -1, -1, 
    /**/
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::i64imm, OpTypes::i32imm, 
    /**/
    -1, OpTypes::i64imm, OpTypes::i32imm, -1, OpTypes::i32imm, OpTypes::i32imm, 
    -1, 
    /**/
    -1, OpTypes::i32imm, 
    -1, 
    /**/
    /**/
    /**/
    /**/
    /**/
    -1, OpTypes::i8imm, 
    OpTypes::i16imm, -1, OpTypes::i32imm, 
    /**/
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, 
    OpTypes::type0, 
    OpTypes::type0, -1, 
    OpTypes::type0, -1, 
    OpTypes::type0, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::ptype0, OpTypes::type1, OpTypes::ptype0, OpTypes::ptype2, -1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type2, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::type0, -1, 
    OpTypes::type0, 
    -1, 
    -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, -1, 
    OpTypes::type0, -1, 
    OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::untyped_imm_0, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, 
    OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, -1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    -1, 
    OpTypes::ptype0, -1, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, OpTypes::type2, 
    OpTypes::type0, OpTypes::type1, OpTypes::type2, 
    OpTypes::type0, OpTypes::type1, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, -1, 
    OpTypes::type0, -1, 
    OpTypes::ptype0, OpTypes::type1, OpTypes::i32imm, 
    OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::btarget, OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::btarget, OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    -1, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, -1, 
    OpTypes::btargetS10, 
    OpTypes::btargetS7, 
    OpTypes::btargetS7, 
    OpTypes::btargetS7, 
    OpTypes::btargetS7, 
    OpTypes::calltargetS25, 
    OpTypes::btargetS7, 
    OpTypes::btargetS7, 
    OpTypes::btargetS7, 
    OpTypes::btargetS7, 
    OpTypes::btargetS13, 
    OpTypes::GPR32, -1, 
    OpTypes::btargetS10, 
    OpTypes::btargetS25, 
    OpTypes::GPR32, OpTypes::btargetS8, 
    OpTypes::GPR32, OpTypes::btargetS8, 
    OpTypes::btargetS9, OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::btargetS9, OpTypes::GPR32, OpTypes::immU6, OpTypes::i32imm, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, -1, 
    OpTypes::btargetS10, 
    OpTypes::btargetS21, OpTypes::i32imm, 
    -1, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    -1, 
    -1, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    /**/
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    /**/
    OpTypes::GPR32, 
    OpTypes::GPR32, 
    /**/
    OpTypes::GPR32, 
    OpTypes::GPR32, 
    /**/
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    /**/
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, 
    /**/
    OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, 
    /**/
    OpTypes::GPR32, OpTypes::GPR32, 
    -1, 
    -1, 
    -1, 
    -1, 
    OpTypes::GPR32, 
    OpTypes::GPR32, 
    -1, 
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    /**/
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    -1, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, -1, 
    -1, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, -1, 
    /**/
    OpTypes::GPR32Reduced, 
    /**/
    OpTypes::GPR32Reduced, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32Reduced, -1, 
    -1, 
    OpTypes::GPR32Reduced, -1, 
    OpTypes::GPR32Reduced, -1, 
    OpTypes::GPR32Reduced, -1, 
    OpTypes::GPR32Reduced, -1, 
    -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    -1, 
    OpTypes::GPR32, OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::i32imm, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 
    OpTypes::GPR32, OpTypes::GPR32, -1, 
    OpTypes::GPR32, OpTypes::GPR32, OpTypes::immU6, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace ARC
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRMAP_INFO
#undef GET_INSTRMAP_INFO
namespace llvm {

namespace ARC {

enum AA {
	AA_PostIncAM
};

// getPostIncOpcode
LLVM_READONLY
int getPostIncOpcode(uint16_t Opcode) {
static const uint16_t getPostIncOpcodeTable[][2] = {
  { ARC::LDB_DI_rs9, ARC::LDB_DI_AB_rs9 },
  { ARC::LDB_X_DI_rs9, ARC::LDB_X_DI_AB_rs9 },
  { ARC::LDB_X_rs9, ARC::LDB_X_AB_rs9 },
  { ARC::LDB_rs9, ARC::LDB_AB_rs9 },
  { ARC::LDH_DI_rs9, ARC::LDH_DI_AB_rs9 },
  { ARC::LDH_X_DI_rs9, ARC::LDH_X_DI_AB_rs9 },
  { ARC::LDH_X_rs9, ARC::LDH_X_AB_rs9 },
  { ARC::LDH_rs9, ARC::LDH_AB_rs9 },
  { ARC::LD_DI_rs9, ARC::LD_DI_AB_rs9 },
  { ARC::LD_rs9, ARC::LD_AB_rs9 },
  { ARC::STB_DI_rs9, ARC::STB_DI_AB_rs9 },
  { ARC::STB_rs9, ARC::STB_AB_rs9 },
  { ARC::STH_DI_rs9, ARC::STH_DI_AB_rs9 },
  { ARC::STH_rs9, ARC::STH_AB_rs9 },
  { ARC::ST_DI_rs9, ARC::ST_DI_AB_rs9 },
  { ARC::ST_rs9, ARC::ST_AB_rs9 },
}; // End of getPostIncOpcodeTable

  unsigned mid;
  unsigned start = 0;
  unsigned end = 16;
  while (start < end) {
    mid = start + (end - start)/2;
    if (Opcode == getPostIncOpcodeTable[mid][0]) {
      break;
    }
    if (Opcode < getPostIncOpcodeTable[mid][0])
      end = mid;
    else
      start = mid + 1;
  }
  if (start == end)
    return -1; // Instruction doesn't exist in this table.

  return getPostIncOpcodeTable[mid][1];
}

} // end namespace ARC
} // end namespace llvm
#endif // GET_INSTRMAP_INFO