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|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/PowerPC/PPCGenAsmWriter.inc10692 MRI.getRegClass(PPC::VSFRCRegClassID).contains(MI->getOperand(1).getReg()) &&
10703 MRI.getRegClass(PPC::VSFRCRegClassID).contains(MI->getOperand(1).getReg()) &&
10714 MRI.getRegClass(PPC::VSFRCRegClassID).contains(MI->getOperand(1).getReg()) &&
gen/lib/Target/PowerPC/PPCGenDAGISel.inc21648 /* 53999*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
21659 /* 54025*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36319 /* 93100*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36331 /* 93133*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36349 /* 93174*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36361 /* 93207*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36383 /* 93260*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36395 /* 93292*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36413 /* 93333*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36425 /* 93365*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36443 /* 93406*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36455 /* 93438*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36473 /* 93479*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36485 /* 93511*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36525 /* 93584*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36537 /* 93617*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36555 /* 93658*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36567 /* 93691*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36712 /* 93990*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36724 /* 94023*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36743 /* 94066*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36755 /* 94099*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36917 /* 94456*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36929 /* 94489*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36948 /* 94532*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
36960 /* 94565*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37154 /* 94951*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37157 /* 94962*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37197 /* 95040*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37200 /* 95051*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37219 /* 95095*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37222 /* 95106*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37242 /* 95155*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37245 /* 95166*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37277 /* 95236*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37280 /* 95247*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37320 /* 95325*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37323 /* 95336*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37342 /* 95380*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37345 /* 95391*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37365 /* 95440*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37368 /* 95451*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37388 /* 95501*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
37398 /* 95524*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
38885 /* 98264*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
39631 /* 99960*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
39664 /*100029*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
40948 /*102925*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
40964 /*102969*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
41016 /*103078*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
41032 /*103122*/ OPC_EmitInteger, MVT::i32, PPC::VSFRCRegClassID,
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 2644 static const MCOperandInfo OperandInfo45[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
2646 static const MCOperandInfo OperandInfo47[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
2758 static const MCOperandInfo OperandInfo159[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2759 static const MCOperandInfo OperandInfo160[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2770 static const MCOperandInfo OperandInfo171[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2772 static const MCOperandInfo OperandInfo173[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2866 static const MCOperandInfo OperandInfo267[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2866 static const MCOperandInfo OperandInfo267[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2867 static const MCOperandInfo OperandInfo268[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2867 static const MCOperandInfo OperandInfo268[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2867 static const MCOperandInfo OperandInfo268[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2869 static const MCOperandInfo OperandInfo270[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2869 static const MCOperandInfo OperandInfo270[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2870 static const MCOperandInfo OperandInfo271[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2870 static const MCOperandInfo OperandInfo271[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2877 static const MCOperandInfo OperandInfo278[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2879 static const MCOperandInfo OperandInfo280[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2880 static const MCOperandInfo OperandInfo281[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2880 static const MCOperandInfo OperandInfo281[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2880 static const MCOperandInfo OperandInfo281[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2880 static const MCOperandInfo OperandInfo281[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2884 static const MCOperandInfo OperandInfo285[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2885 static const MCOperandInfo OperandInfo286[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2893 static const MCOperandInfo OperandInfo294[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
2896 static const MCOperandInfo OperandInfo297[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
2899 static const MCOperandInfo OperandInfo300[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 1719 { VSFRC, VSFRCBits, 150, 64, sizeof(VSFRCBits), PPC::VSFRCRegClassID, 1, true },
4502 &PPCMCRegisterClasses[VSFRCRegClassID],
lib/Target/PowerPC/PPCFastISel.cpp 149 return RC->getID() == PPC::VSFRCRegClassID;
lib/Target/PowerPC/PPCInstrInfo.h 474 case PPC::VSFRCRegClassID:
lib/Target/PowerPC/PPCRegisterInfo.cpp 443 case PPC::VSFRCRegClassID: