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reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/X86/X86GenDAGISel.inc
50386 /*106355*/  /*SwitchOpcode*/ 123, TARGET_VAL(ISD::CTTZ_ZERO_UNDEF),// ->106481
gen/lib/Target/X86/X86GenFastISel.inc
 5911   case ISD::CTTZ_ZERO_UNDEF: return fastEmit_ISD_CTTZ_ZERO_UNDEF_r(VT, RetVT, Op0, Op0IsKill);
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 1544   case ISD::CTTZ_ZERO_UNDEF:    return visitCTTZ_ZERO_UNDEF(N);
 8089   if (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ_ZERO_UNDEF, VT)) {
 8091       return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
 8103     return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
20158              Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 2674   case ISD::CTTZ_ZERO_UNDEF:
 4139   case ISD::CTTZ_ZERO_UNDEF:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
   66   case ISD::CTTZ_ZERO_UNDEF:
 1696   case ISD::CTTZ_ZERO_UNDEF:
 2531   SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  391   case ISD::CTTZ_ZERO_UNDEF:
  806   case ISD::CTTZ_ZERO_UNDEF:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
   79   case ISD::CTTZ_ZERO_UNDEF:
  890   case ISD::CTTZ_ZERO_UNDEF:
 2892   case ISD::CTTZ_ZERO_UNDEF:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 2895   case ISD::CTTZ_ZERO_UNDEF: {
 4337     case ISD::CTTZ_ZERO_UNDEF:
 4448       case ISD::CTTZ_ZERO_UNDEF:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 6206     setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  388   case ISD::CTTZ_ZERO_UNDEF:            return "cttz_zero_undef";
lib/CodeGen/SelectionDAG/TargetLowering.cpp
 6280   if (Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
 6287   if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_UNDEF, VT)) {
 6290     SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op);
lib/CodeGen/TargetLoweringBase.cpp
  679     setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  352   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
 1157   case ISD::CTTZ_ZERO_UNDEF:
 2312   return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
 2318   bool ZeroUndef = Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
 2326     ISDOpc = ISD::CTTZ_ZERO_UNDEF;
lib/Target/AMDGPU/R600ISelLowering.cpp
  247     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
lib/Target/AMDGPU/SIISelLowering.cpp
  386     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
  456     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp
  883     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
  884     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
  885     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
  886     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
  888     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
  889     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
  890     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
  891     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
 5911         (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
 9188   case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
lib/Target/BPF/BPFISelLowering.cpp
  114   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
lib/Target/X86/X86ISelLowering.cpp
  340   setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i8   , MVT::i32);
  344     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16  , Legal);
  345     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32  , Legal);
  348       setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
27745   case ISD::CTTZ_ZERO_UNDEF:    return LowerCTTZ(Op, Subtarget, DAG);
37781         (Add.getOperand(0).getOpcode() == ISD::CTTZ_ZERO_UNDEF ||