reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 2272     if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
 3118     if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
 3122       Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
 3851   case ISD::FSINCOS:

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  198   case ISD::FSINCOS:                    return "fsincos";

lib/Target/AArch64/AArch64ISelLowering.cpp

  249   setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
  377   setOperationAction(ISD::FSINCOS, MVT::f16,   Promote);
  378   setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
  379   setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
  521     setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
  522     setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
  524     setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
  525     setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
  678     setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
 3065   case ISD::FSINCOS:

lib/Target/AMDGPU/SIISelLowering.cpp

 8775   case ISD::FSINCOS:

lib/Target/ARM/ARMISelLowering.cpp

 1302   setOperationAction(ISD::FSINCOS,   MVT::f64, Expand);
 1303   setOperationAction(ISD::FSINCOS,   MVT::f32, Expand);
 1337     setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
 1338     setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
 1376     setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
 9228   case ISD::FSINCOS:       return LowerFSINCOS(Op, DAG);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1383        {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
 1432     ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,

lib/Target/Mips/MipsISelLowering.cpp

  440   setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);
  441   setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);

lib/Target/Mips/MipsSEISelLowering.cpp

  149     setOperationAction(ISD::FSINCOS, MVT::f16, Promote);

lib/Target/PowerPC/PPCISelLowering.cpp

  274   setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
  279   setOperationAction(ISD::FSINCOS, MVT::f32, Expand);

lib/Target/RISCV/RISCVISelLowering.cpp

  149       ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,

lib/Target/Sparc/SparcISelLowering.cpp

 1618   setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
 1623   setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
 1628   setOperationAction(ISD::FSINCOS, MVT::f32, Expand);

lib/Target/SystemZ/SystemZISelLowering.cpp

  434       setOperationAction(ISD::FSINCOS, VT, Expand);

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

   93          {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})

lib/Target/X86/X86ISelLowering.cpp

  546       setOperationAction(ISD::FSINCOS, VT, Expand);
  577     setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
  583       setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
  598       setOperationAction(ISD::FSINCOS, VT, Expand);
  650     setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
  683     setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
  731     setOperationAction(ISD::FSINCOS,   VT, Expand);
 1811     setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
 1812     setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
27775   case ISD::FSINCOS:            return LowerFSINCOS(Op, Subtarget, DAG);