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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc114833 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
gen/lib/Target/ARM/ARMGenDAGISel.inc54379 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
gen/lib/Target/AVR/AVRGenDAGISel.inc 1658 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
gen/lib/Target/PowerPC/PPCGenDAGISel.inc44196 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
include/llvm/CodeGen/BasicTTIImpl.h 179 return ISD::PRE_INC;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp13512 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
13520 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
13873 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB);
20490 Offset = (LSN->getAddressingMode() == ISD::PRE_INC)
lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp 178 if (N->getAddressingMode() == ISD::PRE_INC) {
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 448 case ISD::PRE_INC: return "<pre-inc>";
lib/CodeGen/TargetLoweringBase.cpp 623 for (unsigned IM = (unsigned)ISD::PRE_INC;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 1156 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
lib/Target/AArch64/AArch64ISelLowering.cpp 558 for (unsigned im = (unsigned)ISD::PRE_INC;
888 for (unsigned im = (unsigned)ISD::PRE_INC;
11898 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
lib/Target/ARM/ARMISelDAGToDAG.cpp 767 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
803 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
823 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
902 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
1306 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1359 ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1477 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1584 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1636 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
lib/Target/ARM/ARMISelLowering.cpp 295 for (unsigned im = (unsigned)ISD::PRE_INC;
321 for (unsigned im = (unsigned)ISD::PRE_INC;
375 for (unsigned im = (unsigned)ISD::PRE_INC;
1000 for (unsigned im = (unsigned)ISD::PRE_INC;
15298 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 4466 ST->getAddressingMode() != ISD::PRE_INC)
4477 if (LD->getAddressingMode() != ISD::PRE_INC) {
lib/Target/PowerPC/PPCISelLowering.cpp 172 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
173 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
174 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
175 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
176 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
177 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
178 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
179 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
180 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
181 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
183 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
184 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
185 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
186 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
976 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
977 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
1021 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
1022 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
2578 AM = ISD::PRE_INC;
2601 AM = ISD::PRE_INC;
2627 AM = ISD::PRE_INC;
7529 assert(LD->getAddressingMode() == ISD::PRE_INC &&
9747 assert(LN->getAddressingMode() == ISD::PRE_INC &&
9839 assert(SN->getAddressingMode() == ISD::PRE_INC &&
13583 assert(LD->getAddressingMode() == ISD::PRE_INC &&