reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

61023 /*133348*/        OPC_CheckChild2CondCode, ISD::SETO,
61480 /*134445*/        OPC_CheckChild2CondCode, ISD::SETO,
61950 /*135568*/        OPC_CheckChild2CondCode, ISD::SETO,

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

30340 /* 58590*/          OPC_CheckChild2CondCode, ISD::SETO,
30495 /* 58936*/          OPC_CheckChild2CondCode, ISD::SETO,

gen/lib/Target/Mips/MipsGenDAGISel.inc

17304 /* 32317*/        OPC_CheckChild2CondCode, ISD::SETO,
17344 /* 32413*/        OPC_CheckChild2CondCode, ISD::SETO,
17557 /* 32830*/        OPC_CheckChild2CondCode, ISD::SETO,
17597 /* 32926*/        OPC_CheckChild2CondCode, ISD::SETO,
17980 /* 33675*/        OPC_CheckChild2CondCode, ISD::SETO,
18083 /* 33866*/        OPC_CheckChild2CondCode, ISD::SETO,

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

63504 /*133990*/      OPC_CheckChild2CondCode, ISD::SETO,
63528 /*134038*/      OPC_CheckChild2CondCode, ISD::SETO,
63552 /*134086*/      OPC_CheckChild2CondCode, ISD::SETO,
63566 /*134113*/      OPC_CheckChild2CondCode, ISD::SETO,
63580 /*134140*/      OPC_CheckChild2CondCode, ISD::SETO,
63604 /*134188*/      OPC_CheckChild2CondCode, ISD::SETO,
63628 /*134236*/      OPC_CheckChild2CondCode, ISD::SETO,
63642 /*134263*/      OPC_CheckChild2CondCode, ISD::SETO,
65896 /*139198*/      OPC_CheckChild2CondCode, ISD::SETO,
65925 /*139262*/      OPC_CheckChild2CondCode, ISD::SETO,
65954 /*139326*/      OPC_CheckChild2CondCode, ISD::SETO,
65983 /*139390*/      OPC_CheckChild2CondCode, ISD::SETO,
67363 /*142408*/        OPC_CheckChild2CondCode, ISD::SETO,
68031 /*143843*/        OPC_CheckChild2CondCode, ISD::SETO,
68371 /*144586*/        OPC_CheckChild2CondCode, ISD::SETO,

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

 5855 /* 13675*/              OPC_CheckChild2CondCode, ISD::SETO,
 6405 /* 15177*/              OPC_CheckChild2CondCode, ISD::SETO,
 6955 /* 16679*/              OPC_CheckChild2CondCode, ISD::SETO,
 9510 /* 23441*/              OPC_CheckChild2CondCode, ISD::SETO,
10060 /* 24943*/              OPC_CheckChild2CondCode, ISD::SETO,
10610 /* 26445*/              OPC_CheckChild2CondCode, ISD::SETO,
12170 /* 31218*/            OPC_CheckChild2CondCode, ISD::SETO,
12720 /* 32967*/            OPC_CheckChild2CondCode, ISD::SETO,
13270 /* 34716*/            OPC_CheckChild2CondCode, ISD::SETO,
19853 /* 50271*/            OPC_CheckChild2CondCode, ISD::SETO,
20026 /* 50772*/            OPC_CheckChild2CondCode, ISD::SETO,
20199 /* 51273*/            OPC_CheckChild2CondCode, ISD::SETO,
26206 /* 63317*/        OPC_CheckChild2CondCode, ISD::SETO,
26562 /* 64301*/        OPC_CheckChild2CondCode, ISD::SETO,
26858 /* 65141*/        OPC_CheckChild2CondCode, ISD::SETO,
26965 /* 65391*/        OPC_CheckChild2CondCode, ISD::SETO,
27175 /* 65920*/        OPC_CheckChild2CondCode, ISD::SETO,

gen/lib/Target/RISCV/RISCVGenDAGISel.inc

 7302 /* 13592*/        OPC_CheckChild2CondCode, ISD::SETO,
 7523 /* 14072*/        OPC_CheckChild2CondCode, ISD::SETO,

lib/CodeGen/Analysis.cpp

  210   case FCmpInst::FCMP_ORD:   return ISD::SETO;

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 1672     case ISD::SETO:
 1696           CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
 1715     if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 1986   case ISD::SETO:
 2074     case ISD::SETO:   return getBoolConstant(R!=APFloat::cmpUnordered, dl, VT,

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  406     case ISD::SETO:                     return "seto";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

  328   case ISD::SETO:
 3704     if (Cond == ISD::SETO || Cond == ISD::SETUO)
 3769     ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;

lib/Target/AArch64/AArch64ISelLowering.cpp

 1485   case ISD::SETO:
 1562   case ISD::SETO:

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 1281   case ISD::SETO:

lib/Target/AMDGPU/R600ISelLowering.cpp

  122   setCondCodeAction(ISD::SETO,   MVT::f32, Expand);

lib/Target/AMDGPU/SIISelLowering.cpp

 8301     if (LCC == ISD::SETO) {
 8339     if ((LCC == ISD::SETO || LCC == ISD::SETUO) && Mask &&
 8343       unsigned NewMask = LCC == ISD::SETO ?

lib/Target/AMDGPU/SIInsertSkips.cpp

  219     case ISD::SETO:

lib/Target/ARM/ARMISelLowering.cpp

 1828   case ISD::SETO:   CondCode = ARMCC::VC; break;
 4646   if (CC == ISD::SETO) {
 6247     case ISD::SETO: {

lib/Target/Lanai/LanaiISelLowering.cpp

  858   case ISD::SETO:

lib/Target/Mips/MipsISelLowering.cpp

  623   case ISD::SETO:   return Mips::FCOND_OR;

lib/Target/Mips/MipsSEISelLowering.cpp

 1843                         Op->getOperand(2), ISD::SETO);

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

  554     case ISD::SETO:

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 3855   case ISD::SETO:   return PPC::PRED_NU;
 3883   case ISD::SETO:   Invert = true; return 3;   // !Bit #3 = SETO

lib/Target/PowerPC/PPCISelLowering.cpp

  482     setCondCodeAction(ISD::SETO, MVT::f32, Expand);
  483     setCondCodeAction(ISD::SETO, MVT::f64, Expand);
  744     setCondCodeAction(ISD::SETO,   MVT::v4f32, Expand);
  783       setCondCodeAction(ISD::SETO,   MVT::v2f64, Expand);

lib/Target/Sparc/SparcISelLowering.cpp

 1402   case ISD::SETO:   return SPCC::FCC_O;

lib/Target/SystemZ/SystemZISelLowering.cpp

 1950   case ISD::SETO:  return SystemZ::CCMASK_CMP_O;
 2693   case ISD::SETO: {

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

   88     for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,

lib/Target/X86/X86ISelLowering.cpp

 4757   case ISD::SETO:    return X86::COND_NP;
20477   case ISD::SETO:   SSECC = 7; break;