reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

50420 /*108386*/        OPC_CheckChild2CondCode, ISD::SETONE,
50448 /*108462*/        OPC_CheckChild2CondCode, ISD::SETONE,
50922 /*109755*/        OPC_CheckChild2CondCode, ISD::SETONE,
50950 /*109831*/        OPC_CheckChild2CondCode, ISD::SETONE,
51424 /*111124*/        OPC_CheckChild2CondCode, ISD::SETONE,
51452 /*111200*/        OPC_CheckChild2CondCode, ISD::SETONE,
60987 /*133260*/        OPC_CheckChild2CondCode, ISD::SETONE,
61444 /*134357*/        OPC_CheckChild2CondCode, ISD::SETONE,
61910 /*135472*/        OPC_CheckChild2CondCode, ISD::SETONE,

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

30324 /* 58554*/          OPC_CheckChild2CondCode, ISD::SETONE,
30479 /* 58900*/          OPC_CheckChild2CondCode, ISD::SETONE,

gen/lib/Target/Mips/MipsGenDAGISel.inc

17294 /* 32293*/        OPC_CheckChild2CondCode, ISD::SETONE,
17334 /* 32389*/        OPC_CheckChild2CondCode, ISD::SETONE,
17547 /* 32806*/        OPC_CheckChild2CondCode, ISD::SETONE,
17587 /* 32902*/        OPC_CheckChild2CondCode, ISD::SETONE,
17973 /* 33662*/        OPC_CheckChild2CondCode, ISD::SETONE,
18076 /* 33853*/        OPC_CheckChild2CondCode, ISD::SETONE,

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

61528 /*130090*/      OPC_CheckChild2CondCode, ISD::SETONE,
61552 /*130138*/      OPC_CheckChild2CondCode, ISD::SETONE,
61576 /*130186*/      OPC_CheckChild2CondCode, ISD::SETONE,
61590 /*130213*/      OPC_CheckChild2CondCode, ISD::SETONE,
61604 /*130240*/      OPC_CheckChild2CondCode, ISD::SETONE,
61628 /*130288*/      OPC_CheckChild2CondCode, ISD::SETONE,
61652 /*130336*/      OPC_CheckChild2CondCode, ISD::SETONE,
61666 /*130363*/      OPC_CheckChild2CondCode, ISD::SETONE,
64388 /*135870*/      OPC_CheckChild2CondCode, ISD::SETONE,
64417 /*135934*/      OPC_CheckChild2CondCode, ISD::SETONE,
64446 /*135998*/      OPC_CheckChild2CondCode, ISD::SETONE,
64475 /*136062*/      OPC_CheckChild2CondCode, ISD::SETONE,
66908 /*141433*/        OPC_CheckChild2CondCode, ISD::SETONE,
67602 /*142920*/        OPC_CheckChild2CondCode, ISD::SETONE,
68176 /*144157*/        OPC_CheckChild2CondCode, ISD::SETONE,

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

26953 /* 65358*/        OPC_CheckChild2CondCode, ISD::SETONE,
27163 /* 65887*/        OPC_CheckChild2CondCode, ISD::SETONE,

lib/CodeGen/Analysis.cpp

  209   case FCmpInst::FCMP_ONE:   return ISD::SETONE;
  226     case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE;

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 1685     case ISD::SETONE:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 1985   case ISD::SETONE:
 2050     case ISD::SETONE: return getBoolConstant(R==APFloat::cmpGreaterThan ||

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  404     case ISD::SETONE:                   return "setone";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

  333   case ISD::SETONE:
 3734           if (Cond == ISD::SETONE &&
 3747           if (Cond == ISD::SETONE &&

lib/Target/AArch64/AArch64ISelLowering.cpp

 1481   case ISD::SETONE:
 1528   case ISD::SETONE:
 5182       else if ((CC == ISD::SETNE || CC == ISD::SETONE || CC == ISD::SETUNE) &&

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 1271   case ISD::SETONE:
 2050   SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
 2276   SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);

lib/Target/AMDGPU/R600ISelLowering.cpp

  128   setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
 1039     case ISD::SETONE:

lib/Target/AMDGPU/SIISelLowering.cpp

 9841   if ((CC == ISD::SETOEQ || CC == ISD::SETONE) && LHS.getOpcode() == ISD::FABS) {

lib/Target/AMDGPU/SIInsertSkips.cpp

  215     case ISD::SETONE:

lib/Target/ARM/ARMISelLowering.cpp

 1827   case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
 6235     case ISD::SETONE: {

lib/Target/Lanai/LanaiISelLowering.cpp

  850   case ISD::SETONE:

lib/Target/Mips/MipsISelLowering.cpp

  625   case ISD::SETONE: return Mips::FCOND_ONE;

lib/Target/Mips/MipsSEISelLowering.cpp

 1839                         Op->getOperand(2), ISD::SETONE);

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

  552     case ISD::SETONE:

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 3838   case ISD::SETONE:
 3887   case ISD::SETONE:

lib/Target/PowerPC/PPCISelLowering.cpp

  497   setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
  498   setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
  745     setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
  784       setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
  897         setCondCodeAction(ISD::SETONE, MVT::f128, Expand);

lib/Target/RISCV/RISCVISelLowering.cpp

  144       ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,

lib/Target/Sparc/SparcISelLowering.cpp

 1403   case ISD::SETONE: return SPCC::FCC_LG;

lib/Target/SystemZ/SystemZISelLowering.cpp

 1944   CONV(NE);
 2705   case ISD::SETONE: {

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

   88     for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,

lib/Target/X86/X86ISelLowering.cpp

 4754   case ISD::SETONE:
20479   case ISD::SETONE: SSECC = 12; break;
20667         assert(Cond == ISD::SETONE);