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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 766 OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
lib/CodeGen/SelectionDAG/FastISel.cpp 1022 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
lib/Target/AArch64/AArch64A53Fix835769.cpp 183 BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0);
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 279 BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc))
lib/Target/AArch64/AArch64ConditionalCompares.cpp 695 MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
708 BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 621 BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::SI_IF_BREAK))
730 MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode))
764 return BuildMI(BB, Insert, DL, TII.get(Opcode))
1072 BuildMI(*BB, &I, I.getDebugLoc(),
1593 BuildMI(*BB, &I, DL, TII.get(BrOpcode))
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 201 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII.get(AMDGPU::S_NOP))
896 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
941 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::V_NOP_e32));
1068 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1128 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 685 BuildMI(MBB, Alu, MBB.findDebugLoc((MachineBasicBlock::iterator)Alu),
lib/Target/AMDGPU/SIISelLowering.cpp 3712 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_CMP_EQ_U32))
lib/Target/AMDGPU/SIInsertSkips.cpp 256 BuildMI(MBB, &MI, DL, TII->get(Opcode))
260 auto I = BuildMI(MBB, &MI, DL, TII->get(Opcode));
lib/Target/AMDGPU/SILowerControlFlow.cpp 405 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
lib/Target/AMDGPU/SIModeRegister.cpp 198 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32))
lib/Target/ARC/ARCBranchFinalize.cpp 117 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
132 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
136 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc))
lib/Target/ARM/ARMConstantIslandPass.cpp 1918 MachineInstrBuilder MIB = BuildMI(*MBB, Br.MI, Br.MI->getDebugLoc(),
1973 BuildMI(*MBB, Br.MI, Br.MI->getDebugLoc(), TII->get(Cmp.NewOpc))
lib/Target/ARM/ARMLowOverheadLoops.cpp 362 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
373 MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
395 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
420 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
434 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
452 BuildMI(*MBB, InsertPt, InsertPt->getDebugLoc(), TII->get(Opc));
470 MachineInstrBuilder MIB = BuildMI(*MBB, End, End->getDebugLoc(),
lib/Target/ARM/MLxExpansionPass.cpp 297 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
lib/Target/ARM/MVEVPTBlockPass.cpp 236 MIBuilder = BuildMI(Block, MI, dl, TII->get(NewOpcode));
243 MIBuilder = BuildMI(Block, MI, dl, TII->get(ARM::MVE_VPST));
lib/Target/ARM/Thumb2SizeReduction.cpp 480 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1))
582 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
651 BuildMI(MBB, MI, MI->getDebugLoc(),
823 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
915 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
lib/Target/Hexagon/HexagonFrameLowering.cpp 725 MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
lib/Target/Hexagon/HexagonSplitDouble.cpp 598 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc));
661 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
665 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
lib/Target/Mips/MicroMipsSizeReduction.cpp 711 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 132 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR64))
140 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR))
145 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu))
lib/Target/PowerPC/PPCExpandISEL.cpp 234 BuildMI(*MBB, (*I), dl, TII->get(isISEL8(**I) ? PPC::OR8 : PPC::OR))
311 BuildMI(*MBB, (*MI), dl, TII->get(isISEL8(**MI) ? PPC::OR8 : PPC::OR))
421 BuildMI(*MBB, BIL.back(), dl, TII->get(PPC::BC))
lib/Target/SystemZ/SystemZLongBranch.cpp 358 BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
362 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
377 BuildMI(*MBB, MI, DL, TII->get(CompareOpcode))
380 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 158 BuildMI(MBB, TI, TI->getDebugLoc(), TII.get(WebAssembly::BR))
173 BuildMI(MBB, TI, TI->getDebugLoc(), TII.get(WebAssembly::RETHROW))
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp 202 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 418 BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode))
lib/Target/X86/X86CallFrameOptimization.cpp 533 Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode)).add(PushOp);
560 Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode));
569 Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode))
lib/Target/X86/X86CondBrFolding.cpp 227 BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI), TII->get(X86::JCC_1))
253 MachineInstrBuilder MIB = BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI),
lib/Target/X86/X86DomainReassignment.cpp 155 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(DstOpcode));
192 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY))
270 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
lib/Target/X86/X86InstrInfo.cpp 851 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))