reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/ScheduleDAG.h

  201       return getKind() == Order && Contents.OrdKind == Artificial;

lib/CodeGen/MachinePipeliner.cpp

 1340           Src->addPred(SDep(I, SDep::Artificial));

lib/CodeGen/MachineScheduler.cpp

 1588         DAG->addEdge(Succ.getSUnit(), SDep(SUb, SDep::Artificial));

lib/CodeGen/MacroFusion.cpp

   84       DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial));
   96       DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial));
  104           DAG.addEdge(&FirstSU, SDep(&SU, SDep::Artificial));

lib/CodeGen/ScheduleDAG.cpp

   99     case Artificial:   dbgs() << " Artificial"; break;

lib/CodeGen/ScheduleDAGInstrs.cpp

  256         Dep = SDep(SU, SDep::Artificial);
  873       SDep Dep(SU, SDep::Artificial);

lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

  597           AddPred(TrySU, SDep(Copies.front(), SDep::Artificial));
  604         AddPred(NewDef, SDep(TrySU, SDep::Artificial));

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

 1193   AddPredQueued(NewSU, SDep(SU, SDep::Artificial));
 1251       AddPredQueued(SuccSU, SDep(CopyFromSU, SDep::Artificial));
 1526       AddPredQueued(TrySU, SDep(BtSU, SDep::Artificial));
 1580       AddPredQueued(TrySU, SDep(Copies.front(), SDep::Artificial));
 1587     AddPredQueued(NewDef, SDep(TrySU, SDep::Artificial));
 3120           scheduleDAG->AddPredQueued(&SU, SDep(SuccSU, SDep::Artificial));

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

  748             SUa->addPred(SDep(SI.getSUnit(), SDep::Artificial));
  754               SI.getSUnit()->addPred(SDep(&SU, SDep::Artificial));
  824       if (SU->addPred(SDep(From, SDep::Artificial), false))
  830           SUv->addPred(SDep(SU, SDep::Artificial), false);

lib/Target/Hexagon/HexagonSubtarget.cpp

  302       SDep A(&S0, SDep::Artificial);