|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
Declarations
include/llvm/CodeGen/SelectionDAGNodes.h 182 inline unsigned getOpcode() const;
References
gen/lib/Target/X86/X86GenDAGISel.inc254409 return (N->getOperand(0).getOpcode() == ISD::SDIVREM &&
include/llvm/CodeGen/SelectionDAG.h 769 if (Op.getOpcode() == ISD::UNDEF) {
785 if (Op.getOpcode() == ISD::UNDEF) {
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 809 if (N.getOpcode() == ISD::SETCC) {
816 if (N.getOpcode() != ISD::SELECT_CC ||
857 if (N.getOpcode() != ISD::BUILD_VECTOR)
874 if (V.getOpcode() != ISD::BUILD_VECTOR)
890 if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD)
942 if (N0.getOpcode() != Opc)
1114 unsigned Opc = Op.getOpcode();
1181 unsigned Opc = Op.getOpcode();
1246 unsigned Opc = Op.getOpcode();
1279 if (Op && Op.getOpcode() != ISD::DELETED_NODE)
1295 unsigned Opc = Op.getOpcode();
1308 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1326 unsigned Opc = Op.getOpcode();
1459 RV.getOpcode() != ISD::DELETED_NODE &&
1751 switch (Op.getOpcode()) {
1925 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
1930 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
2005 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND)
2009 if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
2017 SetCC.getOperand(0).getOpcode() != ISD::AND ||
2046 if (!C || ShiftOp.getOpcode() != ISD::SRL)
2114 if (N0.getOpcode() == ISD::SUB &&
2123 if (N0.getOpcode() == ISD::SUB &&
2135 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2148 if (N0.getOpcode() == ISD::OR &&
2166 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0)))
2170 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2174 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
2178 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
2182 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2182 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2188 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2188 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2194 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2194 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2200 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2200 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2206 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
2206 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
2207 N1.getOperand(0).getOpcode() == ISD::SUB &&
2209 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0),
2213 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2213 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2226 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2247 if (N0.getOpcode() == ISD::ADD ||
2248 N0.getOpcode() == ISD::UADDO ||
2249 N0.getOpcode() == ISD::SADDO) {
2269 N0.getOpcode() == ISD::ADD) {
2277 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2363 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
2363 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
2368 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
2381 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
2381 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
2382 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
2382 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
2386 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT))
2405 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
2424 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2424 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2439 N0.getOpcode() == ISD::ADD && isOneOrOneSplat(N0.getOperand(1))) {
2448 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2455 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2464 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
2472 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2482 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
2558 if (V.getOpcode() != ISD::XOR)
2641 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
2671 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2743 if (Carry1.getOpcode() != ISD::UADDO)
2752 if (Carry0.getOpcode() == ISD::ADDCARRY &&
2755 } else if (Carry0.getOpcode() == ISD::UADDO &&
2819 if ((N0.getOpcode() == ISD::ADD ||
2820 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 &&
2926 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2930 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
2934 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
2938 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
2942 if (N0.getOpcode() == ISD::ADD &&
2952 if (N1.getOpcode() == ISD::ADD) {
2964 if (N0.getOpcode() == ISD::SUB &&
2974 if (N0.getOpcode() == ISD::SUB &&
2984 if (N0.getOpcode() == ISD::ADD &&
2985 (N0.getOperand(1).getOpcode() == ISD::SUB ||
2986 N0.getOperand(1).getOpcode() == ISD::ADD) &&
2988 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0),
2992 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD &&
2992 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD &&
2998 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
2998 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
3004 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse())
3010 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) {
3011 if (N1.getOperand(0).getOpcode() == ISD::SUB &&
3018 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
3043 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) {
3060 if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD &&
3066 if (N1.hasOneUse() && N1.getOpcode() == ISD::ADD &&
3073 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3079 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3088 if (N1.getOpcode() == ISD::ZERO_EXTEND &&
3098 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
3098 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
3126 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
3137 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
3272 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
3439 if (N0.getOpcode() == ISD::SHL &&
3453 if (N0.getOpcode() == ISD::SHL &&
3457 } else if (N1.getOpcode() == ISD::SHL &&
3471 N0.getOpcode() == ISD::ADD &&
3841 if (N1.getOpcode() == ISD::SHL) {
3908 if (N1.getOpcode() == ISD::SHL &&
4085 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType())))
4095 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType())))
4253 unsigned HandOpcode = N0.getOpcode();
4256 assert(HandOpcode == N1.getOpcode() && "Bad input!");
4573 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
4573 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
4608 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4792 switch(Op.getOpcode()) {
4816 EVT VT = Op.getOpcode() == ISD::AssertZext ?
4889 if (And.getOpcode() == ISD ::AND)
4913 if (And.getOpcode() == ISD ::AND)
4996 if (Not.getOpcode() == ISD::ANY_EXTEND)
5005 if (Srl.getOpcode() == ISD::TRUNCATE)
5009 if (Srl.getOpcode() != ISD::SRL || !Srl.hasOneUse() ||
5099 if (N0.getOpcode() == ISD::OR &&
5103 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
5128 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5130 N0.getOperand(0).getOpcode() == ISD::LOAD &&
5132 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
5133 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
5229 if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
5230 (N0.getOpcode() == ISD::ANY_EXTEND &&
5231 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
5255 if (N0.getOpcode() == N1.getOpcode())
5255 if (N0.getOpcode() == N1.getOpcode())
5266 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
5269 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
5272 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND &&
5308 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
5339 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
5339 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
5341 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
5341 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
5343 if (N0.getOpcode() == ISD::AND) {
5356 if (N1.getOpcode() == ISD::AND) {
5366 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
5366 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
5368 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
5368 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
5382 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
5393 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
5447 unsigned Opc = N.getOpcode();
5452 unsigned Opc0 = N0.getOpcode();
5529 if (N.getOpcode() == ISD::OR)
5533 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
5533 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
5570 } else if (N0.getOpcode() == ISD::OR) {
5616 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
5616 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
5642 if (N0.getOpcode() == ISD::AND &&
5643 N1.getOpcode() == ISD::AND &&
5659 if (N0.getOpcode() == ISD::AND) {
5805 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
5821 if (N0.getOpcode() == N1.getOpcode())
5821 if (N0.getOpcode() == N1.getOpcode())
5846 if (Op.getOpcode() == ISD::AND &&
5858 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
5858 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
5894 (OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) &&
5894 (OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) &&
5907 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst &&
5908 ExtractFrom.getOpcode() == ISD::ADD &&
5924 IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant;
5925 if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift)
5932 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) &&
5933 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV)))
5938 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() ||
5938 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() ||
6038 if (Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) {
6051 if (Neg.getOpcode() != ISD::SUB)
6060 if (MaskLoBits && Pos.getOpcode() == ISD::AND) {
6092 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) {
6149 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE &&
6149 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE &&
6198 if (LHSShift.getOpcode() == RHSShift.getOpcode())
6198 if (LHSShift.getOpcode() == RHSShift.getOpcode())
6202 if (RHSShift.getOpcode() == ISD::SHL) {
6254 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
6255 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
6256 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
6257 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
6258 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
6259 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
6260 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
6261 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
6341 switch (Op.getOpcode()) {
6381 return Op.getOpcode() == ISD::ZERO_EXTEND
6443 switch (Value.getOpcode()) {
6510 if (Trunc.getOpcode() != ISD::TRUNCATE)
6516 if (Value.getOpcode() == ISD::SRL ||
6517 Value.getOpcode() == ISD::SRA) {
6800 if (And.getOpcode() != ISD::AND || !And.hasOneUse())
6803 if (Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse())
6903 unsigned N0Opcode = N0.getOpcode();
6961 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB &&
7001 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) {
7001 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) {
7042 if (N0Opcode == N1.getOpcode())
7067 unsigned LogicOpcode = LogicOp.getOpcode();
7080 if (V.getOpcode() != ShiftOpcode || !V.hasOneUse())
7153 switch (LHS.getOpcode()) {
7175 bool IsShiftByConstant = (BinOpLHSVal.getOpcode() == ISD::SHL ||
7176 BinOpLHSVal.getOpcode() == ISD::SRA ||
7177 BinOpLHSVal.getOpcode() == ISD::SRL) &&
7179 bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg ||
7180 BinOpLHSVal.getOpcode() == ISD::SELECT;
7197 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS);
7202 assert(N->getOperand(0).getOpcode() == ISD::AND);
7252 if (N1.getOpcode() == ISD::TRUNCATE &&
7253 N1.getOperand(0).getOpcode() == ISD::AND) {
7258 unsigned NextOp = N0.getOpcode();
7300 if (N0.getOpcode() == ISD::AND) {
7305 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
7333 if (N1.getOpcode() == ISD::TRUNCATE &&
7334 N1.getOperand(0).getOpcode() == ISD::AND) {
7344 if (N0.getOpcode() == ISD::SHL) {
7374 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
7375 N0.getOpcode() == ISD::ANY_EXTEND ||
7376 N0.getOpcode() == ISD::SIGN_EXTEND) &&
7377 N0.getOperand(0).getOpcode() == ISD::SHL) {
7408 SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0));
7418 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
7419 N0.getOperand(0).getOpcode() == ISD::SRL) {
7444 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) &&
7444 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) &&
7453 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0),
7464 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
7491 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
7503 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) &&
7503 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) &&
7512 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1);
7516 if (N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse() &&
7564 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
7578 if (N0.getOpcode() == ISD::SRA) {
7609 if (N0.getOpcode() == ISD::SHL && N1C) {
7647 if (!LegalTypes && N0.getOpcode() == ISD::ADD && N0.hasOneUse() && N1C &&
7648 N0.getOperand(0).getOpcode() == ISD::SHL &&
7676 if (N1.getOpcode() == ISD::TRUNCATE &&
7677 N1.getOperand(0).getOpcode() == ISD::AND) {
7686 if (N0.getOpcode() == ISD::TRUNCATE &&
7687 (N0.getOperand(0).getOpcode() == ISD::SRL ||
7688 N0.getOperand(0).getOpcode() == ISD::SRA) &&
7753 if (N0.getOpcode() == ISD::SRL) {
7781 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
7782 N0.getOperand(0).getOpcode() == ISD::SRL) {
7805 if (N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
7816 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
7842 if (N0.getOpcode() == ISD::SRA)
7847 if (N1C && N0.getOpcode() == ISD::CTLZ &&
7884 if (N1.getOpcode() == ISD::TRUNCATE &&
7885 N1.getOperand(0).getOpcode() == ISD::AND) {
8019 if (N0.getOpcode() == ISD::ABS)
8035 if (N0.getOpcode() == ISD::BSWAP)
8048 if (N0.getOpcode() == ISD::BITREVERSE)
8188 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() ||
8450 if (N0.getOpcode() == ISD::SETCC) {
8470 N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) {
8519 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
8520 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
8521 Cond.getOpcode() == ISD::BUILD_VECTOR);
8697 if (N0.getOpcode() == ISD::SETCC) {
8705 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
8708 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
8749 if (LHS.getOpcode() == ISD::LOAD && LHS.hasOneUse() &&
8780 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
8781 N2.getOpcode() == ISD::CONCAT_VECTORS &&
8819 } else if (SCC.getOpcode() == ISD::SETCC) {
8853 if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) {
9165 if (!(N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9165 if (!(N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9166 N0.getOpcode() == ISD::XOR) ||
9167 N0.getOperand(1).getOpcode() != ISD::Constant ||
9168 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT)))
9173 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) ||
9173 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) ||
9174 N1.getOperand(1).getOpcode() != ISD::Constant ||
9175 (LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT)))
9190 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND)
9190 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND)
9207 SDValue Shift = DAG.getNode(N1.getOpcode(), DL1, VT, ExtLoad,
9213 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift,
9251 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() ||
9252 VSel.getOperand(0).getOpcode() != ISD::SETCC)
9385 if (LegalOperations || SetCC.getOpcode() != ISD::SETCC ||
9420 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
9420 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
9423 if (N0.getOpcode() == ISD::TRUNCATE) {
9496 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9496 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9497 N0.getOpcode() == ISD::XOR) &&
9499 N0.getOperand(1).getOpcode() == ISD::Constant &&
9500 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
9515 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
9542 if (N0.getOpcode() == ISD::SETCC) {
9623 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
9625 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND &&
9632 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
9634 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
9655 if (N.getOpcode() != ISD::SETCC ||
9684 if (CtPop.getOpcode() != ISD::CTPOP || !CtPop.hasOneUse())
9708 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
9708 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
9730 if (N0.getOpcode() == ISD::TRUNCATE) {
9774 if (N0.getOpcode() == ISD::AND &&
9775 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
9776 N0.getOperand(1).getOpcode() == ISD::Constant &&
9809 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9809 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9810 N0.getOpcode() == ISD::XOR) &&
9812 N0.getOperand(1).getOpcode() == ISD::Constant &&
9813 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
9821 if (N0.getOpcode() == ISD::AND) {
9840 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
9877 if (N0.getOpcode() == ISD::SETCC) {
9920 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
9920 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
9922 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
9925 if (N0.getOpcode() == ISD::SHL) {
9941 return DAG.getNode(N0.getOpcode(), DL, VT,
9965 if (N0.getOpcode() == ISD::ANY_EXTEND ||
9966 N0.getOpcode() == ISD::ZERO_EXTEND ||
9967 N0.getOpcode() == ISD::SIGN_EXTEND)
9968 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
9972 if (N0.getOpcode() == ISD::TRUNCATE) {
9985 if (N0.getOpcode() == ISD::TRUNCATE)
9990 if (N0.getOpcode() == ISD::AND &&
9991 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
9992 N0.getOperand(1).getOpcode() == ISD::Constant &&
10041 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) &&
10057 if (N0.getOpcode() == ISD::SETCC) {
10111 if (N0.getOpcode() == Opcode &&
10115 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
10116 N0.getOperand(0).getOpcode() == Opcode) {
10139 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
10140 N0.getOperand(0).getOpcode() == ISD::AssertSext &&
10225 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
10277 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
10391 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
10400 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
10400 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
10410 if ((N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
10411 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ||
10412 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) &&
10422 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
10446 if (N0.getOpcode() == ISD::SRL) {
10495 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
10548 if (N0.getOpcode() == ISD::TRUNCATE)
10559 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
10560 N0.getOpcode() == ISD::SIGN_EXTEND ||
10561 N0.getOpcode() == ISD::ANY_EXTEND) {
10564 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
10587 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10613 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) {
10625 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
10645 if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&
10662 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
10663 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
10701 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
10723 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
10767 if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) {
10790 if ((N0.getOpcode() == ISD::ADDE || N0.getOpcode() == ISD::ADDCARRY) &&
10790 if ((N0.getOpcode() == ISD::ADDE || N0.getOpcode() == ISD::ADDCARRY) &&
10793 ((!LegalOperations && N0.getOpcode() == ISD::ADDCARRY) ||
10794 TLI.isOperationLegal(N0.getOpcode(), VT))) {
10799 return DAG.getNode(N0.getOpcode(), SL, VTs, X, Y, N0.getOperand(2));
10806 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
10808 if (N00.getOpcode() == ISD::SIGN_EXTEND ||
10809 N00.getOpcode() == ISD::ZERO_EXTEND ||
10810 N00.getOpcode() == ISD::ANY_EXTEND) {
10825 switch (N0.getOpcode()) {
10838 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) {
10842 return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR);
10852 if (Elt.getOpcode() != ISD::MERGE_VALUES)
10914 switch (N0.getOpcode()) {
10938 LogicOp0.getOpcode() == ISD::BITCAST &&
10942 if (N0.getOpcode() == ISD::OR)
10967 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
10989 if (N0.getOpcode() == ISD::BITCAST)
11033 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
11034 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
11046 if (N0.getOpcode() == ISD::FNEG) {
11050 assert(N0.getOpcode() == ISD::FABS);
11065 if (N0.getOpcode() == ISD::FNEG)
11068 assert(N0.getOpcode() == ISD::FABS);
11084 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
11148 if (N0.getOpcode() == ISD::BUILD_PAIR)
11165 if (Op.getOpcode() == ISD::BITCAST &&
11363 if (N.getOpcode() != ISD::FMUL)
11390 if (N0.getOpcode() == ISD::FP_EXTEND) {
11404 if (N1.getOpcode() == ISD::FP_EXTEND) {
11420 N0.getOpcode() == PreferredFusedOpcode &&
11421 N0.getOperand(2).getOpcode() == ISD::FMUL &&
11434 N1.getOperand(2).getOpcode() == ISD::FMUL &&
11456 if (N0.getOpcode() == PreferredFusedOpcode) {
11458 if (N02.getOpcode() == ISD::FP_EXTEND) {
11485 if (N0.getOpcode() == ISD::FP_EXTEND) {
11487 if (N00.getOpcode() == PreferredFusedOpcode) {
11500 if (N1.getOpcode() == PreferredFusedOpcode) {
11502 if (N12.getOpcode() == ISD::FP_EXTEND) {
11518 if (N1.getOpcode() == ISD::FP_EXTEND) {
11520 if (N10.getOpcode() == PreferredFusedOpcode) {
11575 if (N.getOpcode() != ISD::FMUL)
11597 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) &&
11610 if (N0.getOpcode() == ISD::FP_EXTEND) {
11626 if (N1.getOpcode() == ISD::FP_EXTEND) {
11646 if (N0.getOpcode() == ISD::FP_EXTEND) {
11648 if (N00.getOpcode() == ISD::FNEG) {
11669 if (N0.getOpcode() == ISD::FNEG) {
11671 if (N00.getOpcode() == ISD::FP_EXTEND) {
11690 if (CanFuse && N0.getOpcode() == PreferredFusedOpcode &&
11704 if (CanFuse && N1.getOpcode() == PreferredFusedOpcode &&
11720 if (N0.getOpcode() == PreferredFusedOpcode) {
11722 if (N02.getOpcode() == ISD::FP_EXTEND) {
11745 if (N0.getOpcode() == ISD::FP_EXTEND) {
11747 if (N00.getOpcode() == PreferredFusedOpcode) {
11769 if (N1.getOpcode() == PreferredFusedOpcode &&
11770 N1.getOperand(2).getOpcode() == ISD::FP_EXTEND) {
11795 if (N1.getOpcode() == ISD::FP_EXTEND &&
11796 N1.getOperand(0).getOpcode() == PreferredFusedOpcode) {
11865 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) {
11888 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) {
11966 if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL)
11992 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
11996 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
12007 if (N1CFP && N0.getOpcode() == ISD::FADD &&
12017 if (N0.getOpcode() == ISD::FMUL) {
12029 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
12038 if (N1.getOpcode() == ISD::FMUL) {
12050 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
12059 if (N0.getOpcode() == ISD::FADD) {
12069 if (N1.getOpcode() == ISD::FADD) {
12080 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
12080 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
12151 N1.getOpcode() == ISD::FADD) {
12229 N0.getOpcode() == ISD::FMUL) {
12243 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() &&
12272 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) &&
12272 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) &&
12275 if (Select.getOpcode() != ISD::SELECT)
12283 Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X &&
12373 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) &&
12382 if (N0.getOpcode() == ISD::FMUL &&
12409 if (N0.getOpcode() == ISD::FNEG &&
12428 if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
12560 if (N1.getOpcode() == ISD::FSQRT) {
12563 } else if (N1.getOpcode() == ISD::FP_EXTEND &&
12564 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
12571 } else if (N1.getOpcode() == ISD::FP_ROUND &&
12572 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
12579 } else if (N1.getOpcode() == ISD::FMUL) {
12584 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
12587 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
12652 if ((N1.getOpcode() == ISD::FP_EXTEND ||
12653 N1.getOpcode() == ISD::FP_ROUND)) {
12692 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
12692 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
12693 N0.getOpcode() == ISD::FCOPYSIGN)
12697 if (N1.getOpcode() == ISD::FABS)
12701 if (N1.getOpcode() == ISD::FCOPYSIGN)
12812 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT &&
12816 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT &&
12851 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
12865 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
12866 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
12912 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
12935 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
12935 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
12940 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP;
13013 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
13017 if (N0.getOpcode() == ISD::FP_ROUND) {
13044 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
13072 if (N0.getOpcode() == ISD::FP16_TO_FP &&
13078 if (N0.getOpcode() == ISD::FP_ROUND
13133 switch (N0.getOpcode()) {
13172 N0.getOpcode() == ISD::BITCAST &&
13196 if (N0.getOpcode() == ISD::FMUL &&
13262 if (N0.getOpcode() == ISD::FABS)
13267 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
13267 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
13271 if (!TLI.isFAbsFree(VT) && N0.getOpcode() == ISD::BITCAST && N0.hasOneUse()) {
13309 if (N1.getOpcode() == ISD::SETCC &&
13326 if (N.getOpcode() == ISD::SRL ||
13327 (N.getOpcode() == ISD::TRUNCATE &&
13329 N.getOperand(0).getOpcode() == ISD::SRL))) {
13331 if (N.getOpcode() == ISD::TRUNCATE)
13354 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) {
13354 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) {
13357 if (AndOp1.getOpcode() == ISD::Constant) {
13373 if (N.getOpcode() == ISD::XOR) {
13380 while (N.getOpcode() == ISD::XOR) {
13393 if (N.getOpcode() != ISD::XOR)
13401 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
13401 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
13404 Op0.getOpcode() == ISD::XOR) {
13440 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
13531 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
13531 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
13863 assert((Inc.getOpcode() != ISD::TargetConstant ||
13866 if (Inc.getOpcode() == ISD::TargetConstant) {
14067 bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
14686 if (SliceInst.getOpcode() != ISD::LOAD)
14851 unsigned Opc = Value.getOpcode();
14875 Value.getOperand(1).getOpcode() != ISD::Constant)
15170 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
15171 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) {
15280 bool IsExtractVecSrc = (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
15281 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR);
15350 if (OtherBC.getOpcode() != ISD::EXTRACT_VECTOR_ELT &&
15351 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR)
15512 bool IsExtractVecSrc = (StoredVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
15513 StoredVal.getOpcode() == ISD::EXTRACT_SUBVECTOR);
16046 if (Value.getOpcode() == ISD::TargetConstantFP)
16131 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
16291 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
16291 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
16351 switch (Chain.getOpcode()) {
16426 if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR)
16433 if (Op1.getOpcode() != ISD::SHL) {
16435 if (Op1.getOpcode() != ISD::SHL)
16451 if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() ||
16454 Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() ||
16461 EVT LowTy = (Lo.getOperand(0).getOpcode() == ISD::BITCAST)
16464 EVT HighTy = (Hi.getOperand(0).getOpcode() == ISD::BITCAST)
16503 if (Vec.getOpcode() == ISD::VECTOR_SHUFFLE && Vec.hasOneUse() &&
16504 InsertVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
16543 if (InsertVal.getOpcode() != ISD::BITCAST || !InsertVal.hasOneUse() ||
16601 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
16628 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
16651 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
16767 if (!IndexC || !TLI.isBinOp(Vec.getOpcode()) || !Vec.hasOneUse() ||
16788 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1);
16807 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT &&
16814 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) {
16833 if (IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR &&
16850 if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() &&
16862 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) {
16893 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) {
16911 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
16965 if (VecOp.getOpcode() == ISD::BITCAST) {
17000 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
17027 if (VecOp.getOpcode() == ISD::BITCAST) {
17081 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
17082 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
17132 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
17133 Cast.getOpcode() == ISD::ZERO_EXTEND ||
17310 if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() ||
17311 Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
17407 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
17586 unsigned Opc = Op.getOpcode();
17589 Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
17668 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) &&
17724 if (ISD::BITCAST == Op.getOpcode() &&
17727 else if (ISD::UNDEF == Op.getOpcode())
17788 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
17861 if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse()) {
17872 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR &&
17916 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
17916 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
17928 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
17940 if (ISD::UNDEF == Op.getOpcode())
17943 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
17983 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
18020 if (V.getOpcode() == ISD::INSERT_SUBVECTOR &&
18025 if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS &&
18038 unsigned BinOpcode = BinOp.getOpcode();
18086 unsigned BOpcode = BinOp.getOpcode();
18156 if (V.getOpcode() == ISD::CONCAT_VECTORS && V.getNumOperands() == 2)
18237 if (isNullConstant(Index) && V.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
18249 if (isa<ConstantSDNode>(Index) && V.getOpcode() == ISD::BITCAST &&
18278 if (V.getOpcode() == ISD::CONCAT_VECTORS && isa<ConstantSDNode>(Index) &&
18290 if (V.getOpcode() == ISD::BUILD_VECTOR) {
18326 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) {
18368 if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 ||
18369 N1.getOpcode() != ISD::CONCAT_VECTORS || N1.getNumOperands() != 2 ||
18530 if (S.getOpcode() == ISD::BUILD_VECTOR) {
18532 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) {
18638 unsigned Opcode = N0.getOpcode();
18793 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT)
18902 TLI.isBinOp(N0.getOpcode()) && N0.getNode()->getNumValues() == 1) {
18911 SDValue NewBO = DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR,
18983 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
18986 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
19001 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
19016 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) {
19067 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
19068 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
19091 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && N->isOnlyUserOf(N0.getNode()) &&
19197 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
19254 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
19262 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST &&
19263 N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR &&
19276 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) {
19276 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) {
19293 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR &&
19302 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR &&
19315 if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) &&
19316 N1.getOpcode() == ISD::BITCAST) {
19353 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() &&
19369 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() &&
19458 if (RHS.getOpcode() != ISD::BUILD_VECTOR)
19564 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() &&
19564 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() &&
19564 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() &&
19622 if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() &&
19623 RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() &&
19643 return Concat.getOpcode() == ISD::CONCAT_VECTORS &&
19682 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
19693 if (SCC.getOpcode() == ISD::SELECT_CC) {
19721 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) {
19735 if (Cmp.getOpcode() == ISD::SETCC) {
19755 if (LHS.getOpcode() != RHS.getOpcode() ||
19755 if (LHS.getOpcode() != RHS.getOpcode() ||
19763 if (LHS.getOpcode() == ISD::LOAD) {
19792 LLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex ||
19793 RLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex ||
20157 if ((Count.getOpcode() == ISD::CTTZ ||
20158 Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
20164 if ((Count.getOpcode() == ISD::CTLZ ||
20165 Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) &&
20619 switch (C.getOpcode()) {
20682 if (Chain.getOpcode() == ISD::TokenFactor) {
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 980 Op.getOpcode() == ISD::TargetConstant ||
981 Op.getOpcode() == ISD::Register) &&
3425 if (Tmp1.getOpcode() == ISD::SETCC) {
3484 if (Tmp2.getOpcode() == ISD::SETCC) {
3492 (Tmp2.getOpcode() == ISD::AND &&
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp 524 else if (Cond.getOpcode() == ISD::SETCC) {
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 245 if (Op.getOpcode() == ISD::LOAD) {
273 } else if (Op.getOpcode() == ISD::STORE) {
310 switch (Op.getOpcode()) {
523 switch (Op.getOpcode()) {
542 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
560 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
573 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
580 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
589 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
598 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 1588 if (Mask.getOpcode() == ISD::SETCC) {
1654 if (Mask.getOpcode() == ISD::SETCC) {
2380 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) {
2441 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) {
3816 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
3818 else if (N.getOpcode() == ISD::CONCAT_VECTORS) {
3825 if (N.getOpcode() == ISD::TRUNCATE)
3827 else if (N.getOpcode() == ISD::SIGN_EXTEND)
3830 if (isLogicalMaskOp(N.getOpcode()))
3834 return (N.getOpcode() == ISD::SETCC ||
3928 if (Cond.getOpcode() == ISD::SETCC) {
3964 Cond->getOperand(0).getOpcode() == ISD::SETCC &&
3965 Cond->getOperand(1).getOpcode() == ISD::SETCC) {
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 276 if (ISD::BUILD_VECTOR != Op.getOpcode())
307 if (ISD::BUILD_VECTOR != LHS.getOpcode() ||
308 ISD::BUILD_VECTOR != RHS.getOpcode())
1674 while (V.getOpcode() == ISD::BITCAST)
2142 switch (V.getOpcode()) {
2254 switch (V.getOpcode()) {
2340 unsigned Opcode = V.getOpcode();
2463 unsigned Opcode = Op.getOpcode();
3277 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
3347 if (N0.getOpcode() == ISD::UMUL_LOHI && N0.getResNo() == 1 &&
3351 if (N1.getOpcode() == ISD::UMUL_LOHI && N1.getResNo() == 1) {
3371 if (Val.getOpcode() == ISD::SHL) {
3379 if (Val.getOpcode() == ISD::SRL) {
3386 if (Val.getOpcode() == ISD::BUILD_VECTOR)
3430 unsigned Opcode = Op.getOpcode();
3609 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
3969 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
3969 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
3973 if (Op.getOpcode() == ISD::OR &&
3995 unsigned Opcode = Op.getOpcode();
4118 switch (Op.getOpcode()) {
4167 if (Ops[i].getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4213 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
4239 else if (Op.getOpcode() == ISD::BUILD_VECTOR)
4865 if (!ScalarResult.isUndef() && ScalarResult.getOpcode() != ISD::Constant &&
4866 ScalarResult.getOpcode() != ISD::ConstantFP)
4908 return (Op.isUndef()) || (Op.getOpcode() == ISD::CONDCODE) ||
4967 if (!ScalarResult.isUndef() && ScalarResult.getOpcode() != ISD::Constant &&
4968 ScalarResult.getOpcode() != ISD::ConstantFP)
5060 if (N1.getOpcode() == ISD::EntryToken) return N2;
5061 if (N2.getOpcode() == ISD::EntryToken) return N1;
5244 N1.getOpcode() == ISD::CONCAT_VECTORS &&
5256 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
5270 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
5292 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
5308 if (N1.getOpcode() == ISD::BUILD_PAIR)
5345 if (N2C && N1.getOpcode() == ISD::CONCAT_VECTORS &&
5354 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) &&
5549 if (N1.isUndef() && N2.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
5721 if (Src.getOpcode() == ISD::GlobalAddress)
5723 else if (Src.getOpcode() == ISD::ADD &&
5724 Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
5725 Src.getOperand(1).getOpcode() == ISD::Constant) {
6667 if (Ptr.getOpcode() != ISD::ADD ||
8691 while (V.getOpcode() == ISD::BITCAST)
8697 while (V.getOpcode() == ISD::BITCAST && V.getOperand(0).hasOneUse())
8703 while (V.getOpcode() == ISD::EXTRACT_SUBVECTOR)
8709 if (V.getOpcode() != ISD::XOR)
8974 if (getOpcode() == ISD::TokenFactor) {
9026 return Op.getOpcode() == unsigned(BinOp);
9032 unsigned CandidateBinOp = Op.getOpcode();
9079 if (Op.getOpcode() != CandidateBinOp)
9510 unsigned Opc = Op.getOpcode();
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 1059 if (Root.getOpcode() != ISD::EntryToken) {
5394 switch (N.getOpcode()) {
8488 if (Val.getOpcode() == ISD::MERGE_VALUES) {
9371 assert((Op.getOpcode() != ISD::CopyFromReg ||
9850 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
9867 if (Res.getOpcode() == ISD::AssertZext)
9871 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) {
9880 if (Res.getOpcode() == ISD::CopyFromReg) {
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 2842 if (N.getOpcode() < OpcodeOffset.size())
2843 MatcherIndex = OpcodeOffset[N.getOpcode()];
2868 if (N.getOpcode() < OpcodeOffset.size())
2869 MatcherIndex = OpcodeOffset[N.getOpcode()];
3072 unsigned CurNodeOpcode = N.getOpcode();
lib/CodeGen/SelectionDAG/TargetLowering.cpp 471 unsigned Opcode = Op.getOpcode();
543 Op.getOpcode(), dl, SmallVT,
601 switch (Op.getOpcode()) {
737 if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
778 if (Op.getOpcode() == ISD::Constant) {
807 switch (Op.getOpcode()) {
1058 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1107 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1153 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1290 if (Op0.getOpcode() == ISD::SRL) {
1323 if (Op0.getOpcode() == ISD::ANY_EXTEND) {
1343 if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL &&
1395 if (Op0.getOpcode() == ISD::SHL) {
1497 bool IsFSHL = (Op.getOpcode() == ISD::FSHL);
1626 bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
1659 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG;
1707 bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG;
1745 switch (Src.getOpcode()) {
1939 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
1957 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
1976 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags);
1983 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
2041 assert(DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() &&
2077 if (DAG.getNode(BO.getOpcode(), SDLoc(BO), EltVT, C0, C1).isUndef())
2119 switch (Op.getOpcode()) {
2459 if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG &&
2466 if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) {
2543 if (Op.getOpcode() == ISD::ZERO_EXTEND) {
2551 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
2582 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2583 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2584 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2585 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2617 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2618 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2619 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2620 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2629 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2630 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2631 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2632 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2641 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2642 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2643 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2644 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2655 (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2656 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2657 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2658 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2689 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2690 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2691 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2692 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2785 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
2785 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
2789 if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() ||
2955 unsigned OldShiftOpcode = V.getOpcode();
2982 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
3011 unsigned BOpcode = N0.getOpcode();
3086 if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) &&
3087 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3088 N0.getOperand(1).getOpcode() == ISD::Constant) {
3109 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
3112 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
3213 TopSetCC.getOpcode() == ISD::SETCC &&
3239 N0.getOpcode() == ISD::AND && C1 == 0 &&
3294 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3348 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3381 if (N0.getOpcode() == ISD::SETCC &&
3398 if ((N0.getOpcode() == ISD::XOR ||
3399 (N0.getOpcode() == ISD::AND &&
3400 N0.getOperand(0).getOpcode() == ISD::XOR &&
3412 if (N0.getOpcode() == ISD::XOR) {
3415 assert(N0.getOpcode() == ISD::AND &&
3416 N0.getOperand(0).getOpcode() == ISD::XOR);
3431 if (Op0.getOpcode() == ISD::TRUNCATE)
3434 if ((Op0.getOpcode() == ISD::XOR) &&
3435 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
3436 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
3442 if (Op0.getOpcode() == ISD::AND &&
3459 if (Op0.getOpcode() == ISD::AssertZext &&
3471 if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() &&
3616 N0.getOpcode() == ISD::AND) {
3647 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
3708 if (N0.getOpcode() == ISD::FNEG) {
3778 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3778 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3779 N0.getOpcode() == ISD::XOR) {
3781 if (N0.getOpcode() == N1.getOpcode()) {
3781 if (N0.getOpcode() == N1.getOpcode()) {
3786 if (isCommutativeBinOp(N0.getOpcode())) {
3804 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
3812 if (N0.getOpcode() == ISD::XOR)
3826 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
3850 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3850 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3851 N1.getOpcode() == ISD::XOR)
3860 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) &&
3860 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) &&
3867 if (N0.getOpcode() == ISD::UREM) {
3870 } else if (N0.getOpcode() == ISD::SREM) {
4047 if (Op.getOpcode() == ISD::BasicBlock ||
4048 Op.getOpcode() == ISD::TargetBlockAddress) {
4094 const unsigned OpCode = Op.getOpcode();
4548 if (Op.getNode() && Op.getOpcode() == ISD::TargetBlockAddress)
5346 if (Op.getOpcode() == ISD::FNEG)
5353 if (!Op.hasOneUse() && !(Op.getOpcode() == ISD::FP_EXTEND &&
5361 switch (Op.getOpcode()) {
5421 if (C->isExactlyValue(2.0) && Op.getOpcode() == ISD::FMUL)
5463 if (Op.getOpcode() == ISD::FNEG)
5470 switch (Op.getOpcode()) {
5524 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
5532 Op.getOpcode(), SDLoc(Op), Op.getValueType(), Op.getOperand(0),
5554 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), Neg0,
5561 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
5567 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
7281 assert(Ret.getOpcode() == ISD::MERGE_VALUES &&
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 360 switch (N.getOpcode()) {
377 assert(V.getOpcode() == ISD::SHL && "invalid opcode");
406 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::SHL &&
409 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) {
412 if (LHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(LHS))
414 if (RHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(RHS))
452 if (N.getOpcode() == ISD::SIGN_EXTEND ||
453 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
455 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
469 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
470 N.getOpcode() == ISD::ANY_EXTEND) {
481 } else if (N.getOpcode() == ISD::AND) {
509 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
513 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
549 if (Op1.getOpcode() != ISD::MUL ||
553 if (Op1.getOpcode() != ISD::MUL ||
654 if (N.getOpcode() == ISD::SHL) {
723 if (N.getOpcode() == ISD::FrameIndex) {
742 if (Base.getOpcode() == ISD::FrameIndex) {
757 if (Base.getOpcode() == ISD::FrameIndex) {
784 if (N.getOpcode() == ISD::FrameIndex) {
791 if (N.getOpcode() == AArch64ISD::ADDlow && isWorthFoldingADDlow(N)) {
817 if (Base.getOpcode() == ISD::FrameIndex) {
859 if (Base.getOpcode() == ISD::FrameIndex) {
887 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
920 if (N.getOpcode() != ISD::ADD)
944 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
952 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
1009 if (N.getOpcode() != ISD::ADD)
1057 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
1065 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
2603 if (LN->getOperand(1).getOpcode() != AArch64ISD::ADDlow ||
lib/Target/AArch64/AArch64ISelLowering.cpp 994 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
1030 switch (Op.getOpcode()) {
1055 switch (Op.getOpcode()) {
1598 return Op.getOpcode() == ISD::SUB && isNullConstant(Op.getOperand(0)) &&
1633 } else if (LHS.getOpcode() == ISD::AND && isNullConstant(RHS) &&
1716 } else if (RHS.getOpcode() == ISD::SUB) {
1938 if (V.getOpcode() == ISD::SIGN_EXTEND_INREG)
1941 if (V.getOpcode() == ISD::AND)
1956 unsigned Opc = Op.getOpcode();
2110 switch (Op.getOpcode()) {
2133 bool IsSigned = Op.getOpcode() == ISD::SMULO;
2226 unsigned Opc = Op.getOpcode();
2259 if (Sel.getOpcode() != ISD::SELECT_CC)
2261 if (Sel.getOpcode() != ISD::SELECT_CC)
2323 switch (Op.getOpcode()) {
2449 Op.getOpcode(), dl, Op.getValueType(),
2456 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
2467 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
2484 Op.getOpcode(), dl, Op.getValueType(),
2494 if (Op.getOpcode() == ISD::FP_TO_SINT)
2517 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
2523 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2526 return DAG.getNode(Op.getOpcode(), dl, VT, In);
2543 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
2557 if (Op.getOpcode() == ISD::SINT_TO_FP)
2964 switch (Op.getOpcode()) {
4739 if (LHS.getOpcode() == ISD::AND &&
4755 if (LHS.getOpcode() == ISD::AND &&
4766 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
4776 LHS.getOpcode() != ISD::AND && ProduceNonFlagSettingCondBr) {
5059 } else if (TVal.getOpcode() == ISD::XOR) {
5067 } else if (TVal.getOpcode() == ISD::SUB) {
5241 if (CCVal.getOpcode() == ISD::SETCC) {
5604 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5606 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
5606 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
5662 assert(Op.getOpcode() == ISD::SHL_PARTS);
6255 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
6290 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6946 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
6951 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
6961 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6964 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
7373 if (And.getOpcode() != ISD::AND)
7380 unsigned ShiftOpc = Shift.getOpcode();
7471 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
7590 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7693 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7826 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
7860 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
7964 while (Op.getOpcode() == ISD::BITCAST)
8011 switch (Op.getOpcode()) {
8028 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
8036 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
8220 switch (Op.getOpcode()) {
8478 if (Base.getOpcode() == ISD::ADD &&
8479 Base.getOperand(1).getOpcode() == ISD::SHL &&
8481 Base.getOperand(1).getOperand(1).getOpcode() == ISD::Constant) {
8559 if (Val.getOpcode() != ISD::LOAD)
9227 N->getOperand(0).getOpcode() == ISD::SRL &&
9279 if (Shift.getOpcode() != AArch64ISD::VASHR || !Shift.hasOneUse() ||
9303 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
9304 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
9573 Op.getOpcode() != ISD::FMUL)
9708 if (N.getOpcode() == ISD::SHL)
9710 else if (N.getOpcode() == ISD::SRL)
9778 if (N0.getOpcode() != ISD::AND)
9782 if (N1.getOpcode() != ISD::AND)
9884 if (N0.getOpcode() == ISD::BSWAP) {
10069 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
10114 switch (N.getOpcode()) {
10149 if (N.getOpcode() == ISD::BITCAST)
10151 if (N.getOpcode() != ISD::EXTRACT_SUBVECTOR)
10192 if (Op.getOpcode() == ISD::SETCC) {
10203 if (Op.getOpcode() != AArch64ISD::CSEL)
10236 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
10312 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
10313 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
10314 LHS.getOpcode() != RHS.getOpcode())
10314 LHS.getOpcode() != RHS.getOpcode())
10317 unsigned ExtType = LHS.getOpcode();
10447 if (AndN.getOpcode() != ISD::AND)
10534 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
10692 if (StVal.getOpcode() != ISD::BUILD_VECTOR)
10768 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
11354 if (AddValue.getOpcode() != ISD::ADD)
11417 unsigned CmpOpc = Cmp.getOpcode();
11440 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
11440 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
11441 LHS.getOpcode() == ISD::SRL)
11569 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
11600 if (N0.getOpcode() != ISD::SETCC)
lib/Target/AArch64/AArch64SelectionDAGInfo.cpp 70 if (Ptr.getOpcode() == ISD::FrameIndex) {
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 324 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
330 if (In.getOpcode() != ISD::TRUNCATE)
334 if (Srl.getOpcode() == ISD::SRL) {
349 if (In.getOpcode() == ISD::TRUNCATE) {
954 } else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) &&
958 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
958 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
1180 } else if (Addr.getOpcode() == ISD::SUB) {
1258 } else if (Addr.getOpcode() == ISD::SUB) {
1356 if (N0.getOpcode() == ISD::ADD) {
1938 if (N->getOperand(0).getOpcode() == ISD::SRL) {
1960 if (N->getOperand(0).getOpcode() == ISD::AND) {
1979 } else if (N->getOperand(0).getOpcode() == ISD::SHL) {
1985 if (N->getOperand(0).getOpcode() == ISD::SHL) {
1994 if (Src.getOpcode() != ISD::SRL)
2017 if (Cond.getOpcode() == ISD::CopyToReg)
2020 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
2383 if (Src.getOpcode() == ISD::FNEG) {
2388 if (Src.getOpcode() == ISD::FABS) {
2423 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
2423 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
2464 if (Src.getOpcode() == ISD::FNEG) {
2469 if (Src.getOpcode() == ISD::BUILD_VECTOR) {
2475 if (Lo.getOpcode() == ISD::FNEG) {
2480 if (Hi.getOpcode() == ISD::FNEG) {
2567 if (Src.getOpcode() == ISD::FP_EXTEND) {
2812 } else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) &&
2816 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
2816 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
2832 if (Addr.getOpcode() == ISD::ADD
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1127 switch (Op.getOpcode()) {
2318 bool ZeroUndef = Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
2319 Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF;
2322 if (isCtlzOpc(Op.getOpcode())) {
2325 } else if (isCttzOpc(Op.getOpcode())) {
2346 SDValue HiOrLo = isCtlzOpc(Op.getOpcode()) ? Hi : Lo;
2354 if (isCtlzOpc(Op.getOpcode())) {
2369 SDValue LoOrHi = isCtlzOpc(Op.getOpcode()) ? Lo : Hi;
2509 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2536 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2691 DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2714 DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2960 if (N0.getOpcode() == ISD::TRUNCATE) {
3130 if (LHS.getOpcode() == ISD::AND) {
3173 if (Src.getOpcode() == ISD::BITCAST && !VT.isVector()) {
3175 if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
3192 if (Src.getOpcode() == ISD::SRL && !VT.isVector()) {
3196 if (BV.getOpcode() == ISD::BUILD_VECTOR &&
3218 (Src.getOpcode() == ISD::SRL ||
3219 Src.getOpcode() == ISD::SRA ||
3220 Src.getOpcode() == ISD::SHL)) {
3240 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT,
3296 if (N0.getOpcode() == ISD::ANY_EXTEND)
3299 if (N1.getOpcode() == ISD::ANY_EXTEND)
3436 unsigned Opc = isCttzOpc(RHS.getOpcode()) ? AMDGPUISD::FFBL_B32 :
3442 (isCtlzOpc(RHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3442 (isCtlzOpc(RHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3451 (isCtlzOpc(LHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3451 (isCtlzOpc(LHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3490 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3490 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3491 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3491 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3492 return distributeOpThroughSelect(DCI, LHS.getOpcode(),
3497 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3497 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3504 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3504 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3515 unsigned Opc = NewLHS.getOpcode();
3516 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc))
3518 if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL)
3523 if (LHS.getOpcode() == ISD::FNEG)
3534 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect);
3548 if (Cond.getOpcode() != ISD::SETCC)
3637 unsigned Opc = N0.getOpcode();
3664 if (LHS.getOpcode() != ISD::FNEG)
3669 if (RHS.getOpcode() != ISD::FNEG)
3675 if (Res.getOpcode() != ISD::FADD)
3688 if (LHS.getOpcode() == ISD::FNEG)
3690 else if (RHS.getOpcode() == ISD::FNEG)
3696 if (Res.getOpcode() != Opc)
3712 if (LHS.getOpcode() == ISD::FNEG)
3714 else if (MHS.getOpcode() == ISD::FNEG)
3719 if (RHS.getOpcode() != ISD::FNEG)
3725 if (Res.getOpcode() != Opc)
3755 if (Res.getOpcode() != Opposite)
3767 if (Res.getOpcode() != AMDGPUISD::FMED3)
3784 if (CvtSrc.getOpcode() == ISD::FNEG) {
3801 if (CvtSrc.getOpcode() == ISD::FNEG) {
3841 switch (N0.getOpcode()) {
3888 if (Src.getOpcode() == ISD::BUILD_VECTOR) {
4399 unsigned Opc = Op.getOpcode();
4538 switch (Op.getOpcode()) {
4581 unsigned Opcode = Op.getOpcode();
lib/Target/AMDGPU/AMDGPUISelLowering.h 161 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
lib/Target/AMDGPU/R600ISelLowering.cpp 476 switch (Op.getOpcode()) {
715 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
731 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
769 switch (Op.getOpcode()) {
835 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
1158 bool VectorTrunc = (OldChain.getOpcode() == AMDGPUISD::DUMMY_CHAIN);
1334 if (Ptr.getOpcode() != AMDGPUISD::DWORDADDR) {
1520 if (Ptr.getOpcode() != AMDGPUISD::DWORDADDR) {
1752 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1761 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1860 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1874 if (FNeg.getOpcode() != ISD::FNEG) {
1878 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1922 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1952 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1958 if (Arg.getOpcode() == ISD::BITCAST &&
1959 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
1982 if (LHS.getOpcode() != ISD::SELECT_CC) {
2020 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2038 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
lib/Target/AMDGPU/SIISelLowering.cpp 3950 unsigned Opc = Op.getOpcode();
3970 unsigned Opc = Op.getOpcode();
3991 unsigned Opc = Op.getOpcode();
4014 switch (Op.getOpcode()) {
4307 if (Res.getOpcode() == ISD::MERGE_VALUES) {
7542 if (RHS.getOpcode() == ISD::FSQRT)
7962 switch (Op.getOpcode()) {
8054 if ((N0.getOpcode() != ISD::ADD && N0.getOpcode() != ISD::OR) ||
8054 if ((N0.getOpcode() != ISD::ADD && N0.getOpcode() != ISD::OR) ||
8086 (N0.getOpcode() == ISD::OR ||
8099 if (Ptr.getOpcode() == ISD::SHL) {
8151 switch (V.getOpcode()) {
8197 switch (V.getOpcode()) {
8276 if (LHS.hasOneUse() && LHS.getOpcode() == AMDGPUISD::PERM &&
8292 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == ISD::SETCC) {
8292 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == ISD::SETCC) {
8298 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
8330 if (RHS.getOpcode() == ISD::SETCC && LHS.getOpcode() == AMDGPUISD::FP_CLASS)
8330 if (RHS.getOpcode() == ISD::SETCC && LHS.getOpcode() == AMDGPUISD::FP_CLASS)
8333 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == AMDGPUISD::FP_CLASS &&
8333 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == AMDGPUISD::FP_CLASS &&
8354 (RHS.getOpcode() == ISD::SIGN_EXTEND || LHS.getOpcode() == ISD::SIGN_EXTEND)) {
8354 (RHS.getOpcode() == ISD::SIGN_EXTEND || LHS.getOpcode() == ISD::SIGN_EXTEND)) {
8356 if (RHS.getOpcode() != ISD::SIGN_EXTEND)
8423 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
8424 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
8448 LHS.getOpcode() == AMDGPUISD::PERM &&
8508 if (LHS.getOpcode() == ISD::ZERO_EXTEND &&
8509 RHS.getOpcode() != ISD::ZERO_EXTEND)
8512 if (RHS.getOpcode() == ISD::ZERO_EXTEND) {
8632 if (Src.getOpcode() == ISD::BITCAST) {
8635 fp16SrcZerosHighBits(BCSrc.getOpcode()))
8648 if (((Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_UBYTE &&
8650 (Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_USHORT &&
8667 unsigned Opc = (Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_UBYTE) ?
8704 if (VT == MVT::f32 && (N0.getOpcode() == ISD::UINT_TO_FP ||
8705 N0.getOpcode() == ISD::SINT_TO_FP)) {
8715 unsigned Opcode = Op.getOpcode();
8836 Src.getOpcode() == ISD::TRUNCATE) {
8839 TruncSrc.getOpcode() == ISD::BITCAST &&
8927 if (N0.getOpcode() == ISD::BUILD_VECTOR && VT == MVT::v2f16 &&
8967 unsigned SrcOpc = N0.getOpcode();
8983 return DAG.getNode(N0.getOpcode(), SL, VT, Canon0, Canon1);
9133 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
9146 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
9158 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
9163 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
9169 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) ||
9170 (Opc == ISD::FMINNUM_IEEE && Op0.getOpcode() == ISD::FMAXNUM_IEEE) ||
9172 Op0.getOpcode() == AMDGPUISD::FMAX_LEGACY)) &&
9258 if ((Vec.getOpcode() == ISD::FNEG ||
9259 Vec.getOpcode() == ISD::FABS) && allUsesHaveSourceMods(N)) {
9265 return DAG.getNode(Vec.getOpcode(), SL, EltVT, Elt);
9277 unsigned Opc = Vec.getOpcode();
9448 if (Op1.getOpcode() != Opc || !Op1.hasOneUse())
9488 if ((LHS.getOpcode() == ISD::MUL || RHS.getOpcode() == ISD::MUL)
9488 if ((LHS.getOpcode() == ISD::MUL || RHS.getOpcode() == ISD::MUL)
9492 if (LHS.getOpcode() != ISD::MUL)
9527 unsigned Opc = LHS.getOpcode();
9532 Opc = RHS.getOpcode();
9569 if (LHS.getOpcode() == ISD::SUBCARRY) {
9595 unsigned LHSOpc = LHS.getOpcode();
9621 if (LHS.getOpcode() == ISD::FADD) {
9633 if (RHS.getOpcode() == ISD::FADD) {
9664 if (LHS.getOpcode() == ISD::FADD) {
9678 if (RHS.getOpcode() == ISD::FADD) {
9709 if (FMA.getOpcode() != ISD::FMA ||
9710 Op1.getOpcode() != ISD::FP_EXTEND ||
9711 Op2.getOpcode() != ISD::FP_EXTEND)
9723 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
9724 Op2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9735 if (FMAOp1.getOpcode() != ISD::FP_EXTEND ||
9736 FMAOp2.getOpcode() != ISD::FP_EXTEND)
9741 if (FMAOp1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
9742 FMAOp2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9789 if (VT == MVT::i32 && LHS.getOpcode() == ISD::SIGN_EXTEND &&
9810 LHS.getOpcode() == ISD::SELECT &&
9841 if ((CC == ISD::SETOEQ || CC == ISD::SETONE) && LHS.getOpcode() == ISD::FABS) {
9873 if (Srl.getOpcode() == ISD::ZERO_EXTEND)
9877 if (Srl.getOpcode() == ISD::SRL) {
10238 if (Op.getOpcode() == ISD::AssertZext)
10897 if (Op.getOpcode() == AMDGPUISD::CLAMP) {
lib/Target/ARC/ARCISelDAGToDAG.cpp 77 if (Addr.getOpcode() == ARCISD::GAWRAPPER) {
87 if (Addr.getOpcode() == ARCISD::GAWRAPPER) {
91 if (Addr.getOpcode() != ISD::ADD && Addr.getOpcode() != ISD::SUB &&
91 if (Addr.getOpcode() != ISD::ADD && Addr.getOpcode() != ISD::SUB &&
93 if (Addr.getOpcode() == ISD::FrameIndex) {
107 if (Addr.getOpcode() == ISD::SUB)
114 if (Base.getOpcode() == ISD::FrameIndex) {
131 if (Addr.getOpcode() == ARCISD::GAWRAPPER) {
136 if (Addr.getOpcode() == ISD::SUB)
154 if (Addr.getOpcode() == ISD::ADD) {
lib/Target/ARC/ARCISelLowering.cpp 748 switch (Op.getOpcode()) {
lib/Target/ARM/ARMISelDAGToDAG.cpp 490 assert(N.getOpcode() == ISD::MUL);
534 if (N.getOpcode() == ISD::MUL) {
548 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
572 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
606 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
606 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
608 if (N.getOpcode() == ISD::FrameIndex) {
617 if (N.getOpcode() == ARMISD::Wrapper &&
618 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
619 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
620 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
630 if (N.getOpcode() == ISD::SUB)
635 if (Base.getOpcode() == ISD::FrameIndex) {
655 if (N.getOpcode() == ISD::MUL &&
679 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
679 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
685 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
685 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
693 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
695 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
719 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
722 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
744 if (Offset.getOpcode() == ISD::MUL && N.hasOneUse()) {
774 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
845 if (N.getOpcode() == ISD::SUB) {
856 if (N.getOpcode() == ISD::FrameIndex) {
872 if (Base.getOpcode() == ISD::FrameIndex) {
922 if (N.getOpcode() == ISD::FrameIndex) {
926 } else if (N.getOpcode() == ARMISD::Wrapper &&
927 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
928 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
929 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
943 if (Base.getOpcode() == ISD::FrameIndex) {
1032 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
1052 if (N.getOpcode() != ISD::ADD)
1064 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1095 if (N.getOpcode() == ISD::ADD) {
1097 } else if (N.getOpcode() == ARMISD::Wrapper &&
1098 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
1099 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
1100 N.getOperand(0).getOpcode() != ISD::TargetConstantPool &&
1101 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
1143 if (N.getOpcode() == ISD::FrameIndex) {
1159 if (N.getOperand(0).getOpcode() == ISD::FrameIndex) {
1190 if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
1195 if (N.getOpcode() == ISD::SUB)
1220 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1220 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1222 if (N.getOpcode() == ISD::FrameIndex) {
1231 if (N.getOpcode() == ARMISD::Wrapper &&
1232 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
1233 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
1234 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
1236 if (Base.getOpcode() == ISD::TargetConstantPool)
1250 if (N.getOpcode() == ISD::SUB)
1255 if (Base.getOpcode() == ISD::FrameIndex) {
1274 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1274 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1280 if (N.getOpcode() == ISD::SUB)
1285 if (Base.getOpcode() == ISD::FrameIndex) {
1318 if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
1323 if (Base.getOpcode() == ISD::FrameIndex) {
1329 if (N.getOpcode() == ISD::SUB)
1372 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1390 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1392 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1412 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) {
1435 if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1447 if (Base.getOpcode() == ISD::FrameIndex) {
2787 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2787 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2942 if (Ptr.getOpcode() == ISD::ADD &&
2946 if (Ptr.getOpcode() == ISD::CopyFromReg &&
3173 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
3246 if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI ||
3247 N->getOperand(2).getOpcode() != ARMISD::SUBC ||
3329 assert(N1.getOpcode() == ISD::BasicBlock);
3330 assert(N2.getOpcode() == ISD::Constant);
3331 assert(N3.getOpcode() == ISD::Register);
3335 if (InFlag.getOpcode() == ARMISD::CMPZ) {
3336 if (InFlag.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN) {
3439 if (InFlag.getOpcode() == ARMISD::CMPZ) {
lib/Target/ARM/ARMISelLowering.cpp 1763 if (Op.getOpcode() != ISD::SRL)
1771 if (Op.getOpcode() != ISD::SRA)
1779 if (Op.getOpcode() != ISD::SHL)
2513 if (Arg.getOpcode() == ISD::CopyFromReg) {
2765 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2767 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2769 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
4161 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4220 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4221 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4337 unsigned Opc = Cmp.getOpcode();
4344 Opc = Cmp.getOpcode();
4373 switch (Op.getOpcode()) {
4489 switch (Op.getOpcode()) {
4546 unsigned Opc = Cond.getOpcode();
4569 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4745 if (Op2.getOpcode() != ISD::SELECT_CC)
5180 unsigned Opc = Cond.getOpcode();
5231 unsigned Opc = LHS.getOpcode();
5355 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5365 if (Op.getOpcode() == ISD::FP_TO_SINT)
5408 switch (Op.getOpcode()) {
5430 if (Op.getOpcode() == ISD::SINT_TO_FP)
5451 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5452 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5619 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5675 if (Op.getOpcode() != ISD::CopyFromReg ||
5800 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5802 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
5802 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
5845 assert(Op.getOpcode() == ISD::SHL_PARTS);
5983 while (Op.getOpcode() == ISD::BITCAST)
6289 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
6292 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
7283 if (Lower.getOpcode() == ISD::BUILD_VECTOR)
7287 if (Upper.getOpcode() == ISD::BUILD_VECTOR)
7333 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
7365 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
7825 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
7831 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
8691 if (Op.getOpcode() == ISD::ADDCARRY) {
9012 (PassThru.getOpcode() != ISD::BITCAST ||
9150 switch (Op.getOpcode()) {
10865 if (CC.getValueType() != MVT::i1 || CC.getOpcode() != ISD::SETCC)
10991 if (!(N0.getOpcode() == ISD::SIGN_EXTEND &&
10992 N1.getOpcode() == ISD::SIGN_EXTEND) &&
10993 !(N0.getOpcode() == ISD::ZERO_EXTEND &&
10994 N1.getOpcode() == ISD::ZERO_EXTEND))
11020 if (N0.getOpcode() == ISD::SIGN_EXTEND)
11046 || N0.getOpcode() != ISD::BUILD_VECTOR
11047 || N1.getOpcode() != ISD::BUILD_VECTOR)
11156 if (Mul.getOpcode() != ISD::MUL) {
11159 if (Mul.getOpcode() != ISD::MUL)
11165 if (SRA.getOpcode() != ISD::SRA) {
11168 if (SRA.getOpcode() != ISD::SRA)
11407 if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) {
11410 } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) {
11684 if (U->getOperand(0).getOpcode() == ISD::SHL ||
11685 U->getOperand(1).getOpcode() == ISD::SHL)
11695 if (N->getOperand(0).getOpcode() != ISD::SHL)
11800 unsigned Opcode = N0.getOpcode();
11803 Opcode = N1.getOpcode();
12069 if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) {
12069 if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) {
12079 SRL.getOperand(0).getOpcode() != ISD::SMUL_LOHI)
12175 } else if (N1.getOpcode() == ISD::AND) {
12222 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
12360 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
12366 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
12405 if (N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
12481 while (V.getOpcode() == ARMISD::BFI) {
12516 if (N1.getOpcode() == ISD::AND) {
12534 } else if (N->getOperand(0).getOpcode() == ARMISD::BFI) {
12577 if (InDouble.getOpcode() == ARMISD::VMOVDRR && Subtarget->hasFP64())
12584 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
12620 if (Op0.getOpcode() == ISD::BITCAST)
12622 if (Op1.getOpcode() == ISD::BITCAST)
12624 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
12753 if (V.getOpcode() == ISD::BITCAST &&
12830 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
12831 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
13190 while (Op.getOpcode() == ISD::BITCAST)
13192 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
13192 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
13481 Op.getOpcode() != ISD::FMUL)
13752 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
13831 if (N0.getOpcode() != ISD::LOAD)
13901 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
14202 if (Cmp.getOpcode() != ARMISD::CMPZ)
14218 if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() &&
14242 if (Cmp.getOpcode() != ARMISD::CMPZ)
14293 if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) {
14383 ((FalseVal.getOpcode() == ARMISD::SUBS &&
14693 if (Val.getOpcode() != ISD::LOAD)
15161 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
15385 switch (Op.getOpcode()) {
15460 if (Op.getOpcode() == ARMISD::VGETLANEs)
15481 if (Op.getOpcode() != ISD::AND)
lib/Target/AVR/AVRISelDAGToDAG.cpp 79 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
79 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
88 if (N.getOpcode() == ISD::SUB) {
96 if (N.getOperand(0).getOpcode() == ISD::FrameIndex) {
423 unsigned Op = Callee.getOpcode();
lib/Target/AVR/AVRISelLowering.cpp 288 switch (Op.getOpcode()) {
312 switch (Op.getOpcode()) {
684 switch (Op.getOpcode()) {
lib/Target/BPF/BPFISelDAGToDAG.cpp 108 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
109 Addr.getOpcode() == ISD::TargetGlobalAddress)
478 if (BaseV.getOpcode() != ISD::INTRINSIC_W_CHAIN)
lib/Target/BPF/BPFISelLowering.cpp 191 switch (Op.getOpcode()) {
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 575 if (N->getValueType(0) != MVT::i32 || Shl_1.getOpcode() != ISD::Constant)
581 if (Shl_0.getOpcode() == ISD::MUL) {
598 if (Shl_0.getOpcode() == ISD::SUB) {
602 if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL)
990 if (Op.getOpcode() != ISD::SELECT)
1001 if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
1035 if (Off.getOpcode() != ISD::ADD)
1040 if (T0.getOpcode() != ISD::ADD)
1046 if (T1.getOpcode() != ISD::SHL)
1098 if (Addr.getOpcode() != ISD::ADD)
1102 if (T0.getOpcode() != ISD::AND)
1109 if (S.getOpcode() != ISD::SRL)
1280 if (N.getOpcode() != ISD::FrameIndex)
1330 switch (N.getOpcode()) {
1374 switch (N.getOpcode()) {
1378 unsigned GAOpc = N0.getOpcode();
1439 unsigned Opc = N.getOpcode();
1497 unsigned Opc = Val.getOpcode();
1732 if (Val.getOpcode() != ISD::SHL ||
1759 if (Val.getOpcode() != ISD::MUL ||
1787 if (Val.getOpcode() == ISD::MUL) {
1799 if (Val.getOpcode() == ISD::SHL) {
1810 if (V.getOpcode() == ISD::MUL) {
1818 } else if (V.getOpcode() == ISD::SHL) {
1827 if (V.getOpcode() == ISD::MUL) {
1839 } else if (V.getOpcode() == ISD::SHL) {
1847 return CurDAG->getNode(V.getOpcode(), SDLoc(V), V.getValueType(), Ops);
1851 return V.getOpcode() == HexagonISD::CONST32 ||
1852 V.getOpcode() == HexagonISD::CONST32_GP;
1942 ((isOpcodeHandled(Op0.getNode()) && Op0.getOpcode() == ISD::SHL &&
1944 (isOpcodeHandled(Op1.getNode()) && Op1.getOpcode() == ISD::SHL &&
1978 (Child.getOpcode() == ISD::MUL || Child.getOpcode() == ISD::SHL) &&
1978 (Child.getOpcode() == ISD::MUL || Child.getOpcode() == ISD::SHL) &&
2012 unsigned ChildOpcode = Child.getOpcode();
2090 GA.Value = CurDAG->getNode(GA.Value.getOpcode(), SDLoc(GA.Value),
2201 if (NewRoot.getOpcode() == ISD::MUL) {
2239 if (BasePtr.getOpcode() != ISD::ADD)
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp 949 unsigned AddrOpc = Addr.getOpcode();
951 if (Addr.getOperand(0).getOpcode() == ISD::TargetConstantPool)
lib/Target/Hexagon/HexagonISelLowering.cpp 581 if ((Op.getOpcode() != ISD::INLINEASM &&
582 Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR())
836 switch (N.getOpcode()) {
840 if (Op.getOpcode() != ISD::AssertSext)
1899 if (Addr.getOpcode() == ISD::ADD) {
2042 switch (Op.getOpcode()) {
2704 unsigned BaseOpc = BO.first.getOpcode();
2751 unsigned Opc = Op.getOpcode();
2780 unsigned Opc = Op.getOpcode();
2824 unsigned Opc = Op.getOpcode();
2932 unsigned Opc = Op.getOpcode();
2936 switch (P.getOpcode()) {
3229 if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
lib/Target/Hexagon/HexagonISelLowering.h 360 return Op.getOpcode() == ISD::UNDEF;
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 262 if (Vec.getOpcode() == HexagonISD::QCAT)
419 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1069 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1077 if (V.getOpcode() == ISD::Constant)
1331 bool IsSigned = Op.getOpcode() == ISD::MULHS;
1429 assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG);
1458 if (Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1468 SDValue L = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsL);
1469 SDValue H = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsH);
1519 unsigned Opc = Op.getOpcode();
1591 unsigned Opc = Op.getOpcode();
lib/Target/Lanai/LanaiISelDAGToDAG.cpp 113 if (Addr.getOpcode() == ISD::OR &&
114 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL) {
163 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
164 Addr.getOpcode() == ISD::TargetGlobalAddress))
168 ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode());
192 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL)
214 if (Addr.getOpcode() == ISD::FrameIndex)
218 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
219 Addr.getOpcode() == ISD::TargetGlobalAddress))
223 ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode());
232 if (Addr.getOperand(0).getOpcode() == LanaiISD::HI ||
233 Addr.getOperand(0).getOpcode() == LanaiISD::LO ||
234 Addr.getOperand(0).getOpcode() == LanaiISD::SMALL ||
235 Addr.getOperand(1).getOpcode() == LanaiISD::HI ||
236 Addr.getOperand(1).getOpcode() == LanaiISD::LO ||
237 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL)
lib/Target/Lanai/LanaiISelLowering.cpp 177 switch (Op.getOpcode()) {
1492 switch (Op.getOpcode()) {
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp 186 switch (N.getOpcode()) {
355 if (N1.getOpcode() == ISD::LOAD &&
lib/Target/MSP430/MSP430ISelLowering.cpp 336 switch (Op.getOpcode()) {
945 unsigned Opc = Op.getOpcode();
1040 if (LHS.getOpcode() == ISD::Constant)
1047 if (LHS.getOpcode() == ISD::Constant)
1141 (LHS.getOpcode() == ISD::AND ||
1142 (LHS.getOpcode() == ISD::TRUNCATE &&
1143 LHS.getOperand(0).getOpcode() == ISD::AND))) {
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 112 if (Addr.getOpcode() == MipsISD::Wrapper) {
118 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
119 Addr.getOpcode() == ISD::TargetGlobalAddress))
142 if (Addr.getOpcode() == ISD::ADD) {
151 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
152 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
lib/Target/Mips/MipsISelLowering.cpp 646 if (Op.getOpcode() != ISD::SETCC)
684 if ((SetCC.getOpcode() != ISD::SETCC) ||
789 unsigned FirstOperandOpc = FirstOperand.getOpcode();
879 if (And0.getOpcode() != ISD::AND)
887 if (And1.getOpcode() == ISD::AND &&
888 And1.getOperand(0).getOpcode() == ISD::SHL) {
925 bool isConstCase = And1.getOpcode() != ISD::AND;
926 if (And1.getOpcode() == ISD::AND) {
966 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
967 ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
996 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1000 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1085 if (Add.getOpcode() != ISD::ADD)
1090 if ((Lo.getOpcode() != MipsISD::Lo) ||
1091 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1113 unsigned FirstOperandOpc = FirstOperand.getOpcode();
1219 switch (Op.getOpcode())
1912 if (CondRes.getOpcode() != MipsISD::FPCmp)
1932 if (Cond.getOpcode() != MipsISD::FPCmp)
1943 assert(Cond.getOpcode() == MipsISD::FPCmp &&
2666 if (Val.getOpcode() != ISD::FP_TO_SINT ||
3071 Chain.getOpcode() == ISD::CALLSEQ_START;
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 207 unsigned Opc = InFlag.getOpcode();
317 if (Addr.getOpcode() == MipsISD::Wrapper) {
324 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
325 Addr.getOpcode() == ISD::TargetGlobalAddress))
334 if (Addr.getOpcode() == ISD::ADD) {
343 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
344 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
lib/Target/Mips/MipsSEISelLowering.cpp 450 switch(Op.getOpcode()) {
986 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
1323 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 3411 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
3411 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
3584 if (N.getOpcode() == ISD::TargetGlobalAddress ||
3585 N.getOpcode() == ISD::TargetExternalSymbol) {
3589 if (N.getOpcode() == NVPTXISD::Wrapper) {
3597 CastN->getOperand(0).getOpcode() == NVPTXISD::MoveParam)
3606 if (Addr.getOpcode() == ISD::ADD) {
3639 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
3640 Addr.getOpcode() == ISD::TargetGlobalAddress)
3643 if (Addr.getOpcode() == ISD::ADD) {
lib/Target/NVPTX/NVPTXISelLowering.cpp 1964 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1964 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1972 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2025 assert(Op.getOpcode() == ISD::SHL_PARTS);
2173 switch (Op.getOpcode()) {
4354 if (N0.getOpcode() == ISD::MUL) {
4368 else if (N0.getOpcode() == ISD::FMUL) {
4480 if (Val.getOpcode() == ISD::ANY_EXTEND) {
4584 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4585 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4591 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 225 if (N.getOpcode() == ISD::TargetConstant ||
226 N.getOpcode() == ISD::TargetGlobalAddress) {
630 if (Base.getOpcode() != PPCISD::ADD_TLS)
673 if (Base.getOpcode() != PPCISD::ADD_TLS)
726 unsigned Op0Opc = Op0.getOpcode();
727 unsigned Op1Opc = Op1.getOpcode();
735 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
736 Op0.getOperand(0).getOpcode() == ISD::SRL) {
737 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
738 Op1.getOperand(0).getOpcode() != ISD::SRL) {
745 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
746 Op1.getOperand(0).getOpcode() != ISD::SRL) {
767 unsigned SHOpc = Op1.getOperand(0).getOpcode();
1225 switch (V.getOpcode()) {
2537 if (isLogicOp(N->getOperand(0).getOpcode()) &&
2541 else if (N->getOperand(0).getOpcode() != ISD::SETCC)
2652 assert(isLogicOp(LogicOp.getOpcode()) &&
2667 unsigned OperandOpcode = Operand.getOpcode();
2699 switch (LogicOp.getOpcode()) {
2722 unsigned Opc = Input.getOpcode();
2727 (Input.getOperand(0).getOpcode() == ISD::AssertSext ||
2728 Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND))
2755 unsigned Opc = Input.getOpcode();
2762 (Input.getOperand(0).getOpcode() == ISD::AssertZext ||
2763 Input.getOperand(0).getOpcode() == ISD::ZERO_EXTEND);
3553 assert(Compare.getOpcode() == ISD::SETCC &&
3578 assert((Compare.getOpcode() == ISD::SETCC ||
3579 Compare.getOpcode() == ISD::SELECT_CC) &&
3584 if ((Compare.getOpcode() == ISD::SETCC) && !allUsesExtend(Compare, CurDAG))
3591 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2;
4179 AddrOp.getOpcode() == ISD::ADD ? AddrOp.getOperand(0) :
4190 if (AddrOp.getOpcode() != ISD::ADD)
4194 if (AddrOp.getOpcode() == ISD::ADD)
4198 return AddrOp.getOpcode() == ISD::CopyFromReg;
4231 (TrueResVal == -1 && FalseRes.getOpcode() != ISD::ZERO_EXTEND) ||
4232 (TrueResVal == 1 && FalseRes.getOpcode() != ISD::SIGN_EXTEND) ||
4234 (FalseRes.getOpcode() != ISD::SELECT_CC || CC != ISD::SETEQ)))
4237 bool InnerIsSel = FalseRes.getOpcode() == ISD::SELECT_CC;
4239 if (SetOrSelCC.getOpcode() != ISD::SETCC &&
4240 SetOrSelCC.getOpcode() != ISD::SELECT_CC)
4360 N->getOperand(1).getOpcode() == ISD::TargetConstant)
4486 if (Offset.getOpcode() == ISD::TargetConstant ||
4487 Offset.getOpcode() == ISD::TargetGlobalAddress) {
4586 N->getOperand(0).getOpcode() != ISD::ROTL) {
4600 if (Val.getOpcode() == ISD::ANY_EXTEND) {
4602 if ( Op0.getOpcode() == ISD::SRL &&
4622 if (Val.getOpcode() == ISD::SRL &&
4655 N->getOperand(0).getOpcode() == ISD::OR &&
4950 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5268 if (O.getOpcode() != ISD::SELECT_CC)
5292 if (Op0.getOpcode() == ISD::TRUNCATE)
5294 if (Op1.getOpcode() == ISD::TRUNCATE)
5297 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
5297 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
5320 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
5346 if (Op.getOpcode() == ISD::AND) {
5353 if (XOR.getOpcode() == ISD::TRUNCATE)
5355 if (XOR.getOpcode() != ISD::XOR)
5361 } else if (Op.getOpcode() == ISD::SRL) {
5371 if (XOR.getOpcode() == ISD::TRUNCATE)
5373 if (XOR.getOpcode() != ISD::XOR)
5392 if (O.getOpcode() == ISD::OR) {
lib/Target/PowerPC/PPCISelLowering.cpp 2285 if (N.getOpcode() == ISD::ADD) {
2293 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2299 } else if (N.getOpcode() == ISD::OR) {
2378 if (N.getOpcode() == ISD::ADD) {
2390 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2395 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
2396 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
2397 Disp.getOpcode() == ISD::TargetConstantPool ||
2398 Disp.getOpcode() == ISD::TargetJumpTable);
2402 } else if (N.getOpcode() == ISD::OR) {
2482 if (N.getOpcode() == ISD::ADD &&
4936 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4937 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
5253 assert(((Callee.getOpcode() == ISD::Register &&
5255 Callee.getOpcode() == ISD::TargetExternalSymbol ||
5256 Callee.getOpcode() == ISD::TargetGlobalAddress ||
7358 Op.getOpcode() == ISD::FP_TO_SINT
7364 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
7366 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
7374 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
7422 Op.getOpcode() == ISD::FP_TO_SINT
7429 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
7431 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
7451 if (Op.getOpcode() == ISD::FP_TO_SINT) {
7465 if (Op.getOpcode() == ISD::FP_TO_UINT) {
7511 (Op.getOpcode() == ISD::FP_TO_UINT ||
7512 Op.getOpcode() == ISD::FP_TO_SINT) &&
7513 isOperationLegalOrCustom(Op.getOpcode(),
7613 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
7653 unsigned Opc = Op.getOpcode();
7704 isOperationCustom(Op.getOpcode(), InVT))
7747 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
7753 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
7755 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
7838 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
7840 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
7866 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
7919 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
8210 if (V->getOperand(i).getOpcode() == ISD::LOAD ||
8211 (V->getOperand(i).getOpcode() == ISD::FP_ROUND &&
8212 V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD) ||
8213 (V->getOperand(i).getOpcode() == ISD::FP_TO_SINT &&
8214 V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD) ||
8215 (V->getOperand(i).getOpcode() == ISD::FP_TO_UINT &&
8216 V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD))
8235 (Op0.getOpcode() != ISD::BUILD_PAIR) ||
8246 if (InputLoad->getOpcode() == ISD::BITCAST)
8248 if (InputLoad->getOpcode() == ISD::SCALAR_TO_VECTOR)
8250 if (InputLoad->getOpcode() != ISD::LOAD)
9544 if ((Op.getOpcode() == ISD::SREM && UI->getOpcode() == ISD::SDIV) ||
9545 (Op.getOpcode() == ISD::UREM && UI->getOpcode() == ISD::UDIV))
9574 assert(Op.getOpcode() == ISD::ATOMIC_CMP_SWAP &&
9624 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT &&
9998 assert(Op.getOpcode() == ISD::ABS && "Should only be called for ISD::ABS");
10037 assert(Op.getOpcode() == ISD::FP_EXTEND &&
10048 switch (Op0.getOpcode()) {
10082 if (LdOp.getOpcode() != ISD::LOAD)
10092 DAG.getNode(Op0.getOpcode(), SDLoc(Op0), MVT::v4f32, NewLoad[0],
10113 switch (Op.getOpcode()) {
11728 if (Loc.getOpcode() == ISD::FrameIndex) {
11729 if (BaseLoc.getOpcode() != ISD::FrameIndex)
12077 if (N->getOperand(0).getOpcode() != ISD::AND &&
12078 N->getOperand(0).getOpcode() != ISD::OR &&
12079 N->getOperand(0).getOpcode() != ISD::XOR &&
12080 N->getOperand(0).getOpcode() != ISD::SELECT &&
12081 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
12082 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
12083 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
12084 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
12085 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
12089 N->getOperand(1).getOpcode() != ISD::AND &&
12090 N->getOperand(1).getOpcode() != ISD::OR &&
12091 N->getOperand(1).getOpcode() != ISD::XOR &&
12092 N->getOperand(1).getOpcode() != ISD::SELECT &&
12093 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
12094 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
12095 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
12096 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
12097 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
12105 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
12106 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
12107 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
12131 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
12133 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
12136 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
12137 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
12138 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
12142 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
12143 BinOp.getOperand(i).getOpcode() == ISD::OR ||
12144 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
12145 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
12146 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
12147 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
12148 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
12149 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
12150 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
12237 if (PromOp.getOpcode() == ISD::TRUNCATE ||
12238 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
12239 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
12240 PromOp.getOpcode() == ISD::ANY_EXTEND) {
12257 switch (PromOp.getOpcode()) {
12284 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
12323 if (N->getOperand(0).getOpcode() != ISD::AND &&
12324 N->getOperand(0).getOpcode() != ISD::OR &&
12325 N->getOperand(0).getOpcode() != ISD::XOR &&
12326 N->getOperand(0).getOpcode() != ISD::SELECT &&
12327 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
12347 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
12349 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
12352 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
12355 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
12356 BinOp.getOperand(i).getOpcode() == ISD::OR ||
12357 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
12358 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
12359 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
12491 switch (PromOp.getOpcode()) {
12511 if (PromOp.getOpcode() == ISD::SELECT ||
12512 PromOp.getOpcode() == ISD::SELECT_CC) {
12542 if (PromOp.getOpcode() == ISD::SELECT ||
12543 PromOp.getOpcode() == ISD::SELECT_CC) {
12553 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
12590 if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
12596 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
12635 assert(FirstInput.getOpcode() == PPCISD::MFVSR &&
12640 unsigned FirstConversion = FirstInput.getOperand(0).getOpcode();
12653 if (NextOp.getOpcode() != PPCISD::MFVSR)
12655 unsigned NextConversion = NextOp.getOperand(0).getOpcode();
12728 if (FirstInput.getOpcode() == ISD::FP_ROUND &&
12729 FirstInput.getOperand(0).getOpcode() == ISD::LOAD) {
12734 if ((!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD) ||
12740 if (IsRoundOfExtLoad && N->getOperand(i).getOpcode() != ISD::FP_ROUND)
12745 if (NextInput.getOpcode() != ISD::LOAD)
12862 if (Op.getOpcode() != ISD::SIGN_EXTEND &&
12863 Op.getOpcode() != ISD::SIGN_EXTEND_INREG)
12869 if (Extract.getOpcode() == ISD::ANY_EXTEND)
12871 if (Extract.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12945 if (FirstInput.getOpcode() == PPCISD::MFVSR) {
12973 if (FirstInput.getOpcode() != ISD::SINT_TO_FP &&
12974 FirstInput.getOpcode() != ISD::UINT_TO_FP)
12976 if (N->getOperand(1).getOpcode() != ISD::SINT_TO_FP &&
12977 N->getOperand(1).getOpcode() != ISD::UINT_TO_FP)
12979 if (FirstInput.getOpcode() != N->getOperand(1).getOpcode())
12979 if (FirstInput.getOpcode() != N->getOperand(1).getOpcode())
12984 if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
12985 Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13007 auto NodeType = (N->getOperand(1).getOpcode() == ISD::SINT_TO_FP) ?
13035 bool SubWordLoad = FirstOperand.getOpcode() == ISD::LOAD &&
13070 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
13076 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
13078 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
13086 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
13088 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
13099 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
13257 unsigned Opcode = N->getOperand(1).getOpcode();
13419 unsigned Opcode = N->getOperand(1).getOpcode();
13833 if (V1.getOpcode() == ISD::SUB &&
13839 if (V2.getOpcode() == ISD::SUB &&
13845 if (V1.getOpcode() == ISD::SUB && V2.getOpcode() == ISD::SUB &&
13845 if (V1.getOpcode() == ISD::SUB && V2.getOpcode() == ISD::SUB &&
13973 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
13998 if (LHS.getOpcode() == ISD::AND &&
13999 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
14006 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
14030 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
14133 switch (Op.getOpcode()) {
15139 N0.getOpcode() != ISD::SIGN_EXTEND ||
15147 if (ExtsSrc.getOpcode() == ISD::TRUNCATE &&
15148 ExtsSrc.getOperand(0).getOpcode() == ISD::AssertSext)
15189 if (Op.getOpcode() != ISD::ZERO_EXTEND || !Op.hasOneUse() ||
15194 if (Cmp.getOpcode() != ISD::SETCC || !Cmp.hasOneUse() ||
15298 if (Op0.getOpcode() == ISD::SRL) {
15311 if (Op0.getOpcode() == ISD::BITCAST &&
15481 if (N->getOperand(0).getOpcode() == ISD::SUB) {
15484 unsigned SubOpcd0 = N->getOperand(0)->getOperand(0).getOpcode();
15485 unsigned SubOpcd1 = N->getOperand(0)->getOperand(1).getOpcode();
15527 if (Cond.getOpcode() != ISD::SETCC || TrueOpnd.getOpcode() != ISD::SUB ||
15527 if (Cond.getOpcode() != ISD::SETCC || TrueOpnd.getOpcode() != ISD::SUB ||
15528 FalseOpnd.getOpcode() != ISD::SUB)
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 91 Node->getOperand(1).getOpcode() == ISD::Constant) {
146 if (Op1.getOpcode() == ISD::Constant &&
lib/Target/RISCV/RISCVISelLowering.cpp 370 switch (Op.getOpcode()) {
626 if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC &&
885 if (N->getOperand(1).getOpcode() == ISD::Constant)
894 if (N->getOperand(1).getOpcode() == ISD::Constant)
903 if (N->getOperand(0).getOpcode() == ISD::Constant ||
904 N->getOperand(1).getOpcode() == ISD::Constant)
953 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
953 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
962 if (Op0.getOpcode() == ISD::FNEG) {
967 assert(Op0.getOpcode() == ISD::FABS);
1001 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
1001 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
1007 if (Op0.getOpcode() == ISD::FNEG) {
1012 assert(Op0.getOpcode() == ISD::FABS);
1032 (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR)) {
1032 (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR)) {
1071 switch (Op.getOpcode()) {
lib/Target/Sparc/SparcISelDAGToDAG.cpp 83 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
84 Addr.getOpcode() == ISD::TargetGlobalAddress ||
85 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
88 if (Addr.getOpcode() == ISD::ADD) {
104 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
109 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
121 if (Addr.getOpcode() == ISD::FrameIndex) return false;
122 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
123 Addr.getOpcode() == ISD::TargetGlobalAddress ||
124 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
127 if (Addr.getOpcode() == ISD::ADD) {
131 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
132 Addr.getOperand(1).getOpcode() == SPISD::Lo)
lib/Target/Sparc/SparcISelLowering.cpp 1864 switch (Op.getOpcode()) {
1885 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1886 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1887 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1888 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1889 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2845 return LowerF64Op(Op.getOperand(0), dl, DAG, Op.getOpcode());
2862 Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64);
2864 Lo64 = LowerF64Op(Lo64, dl, DAG, Op.getOpcode());
2867 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2869 Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode());
2901 unsigned hiOpc = Op.getOpcode();
2902 switch (Op.getOpcode()) {
2912 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2915 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2935 unsigned opcode = Op.getOpcode();
3008 switch (Op.getOpcode()) {
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 184 if (SystemZISD::isPCREL(Addr.getOpcode())) {
454 unsigned Opcode = N.getOpcode();
457 Opcode = N.getOpcode();
573 if (Addr.getOpcode() == ISD::Constant &&
578 else if (Addr.getOpcode() == SystemZISD::ADJDYNALLOC &&
630 else if (Base.getOpcode() == ISD::FrameIndex) {
706 if (Index.getOpcode() == ISD::ZERO_EXTEND)
708 if (Index.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
722 if (Op.getOpcode() != ISD::AND)
771 unsigned Opcode = N.getOpcode();
962 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND &&
963 RISBG.Input.getOpcode() != ISD::TRUNCATE)
1068 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND &&
1069 RxSBG[I].Input.getOpcode() != ISD::TRUNCATE)
1208 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1281 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1441 if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode()))
1444 if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode()))
1470 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1476 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1485 Node->getOperand(0).getOpcode() != ISD::Constant)
1491 unsigned ChildOpcode = Node->getOperand(0).getOpcode();
1514 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1544 if ((Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) ||
1544 if ((Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) ||
1547 Op1.getOpcode() == ISD::Constant &&
1549 !(Op0.getOpcode() == ISD::Constant &&
1672 if (Base.getOpcode() != ISD::TargetFrameIndex &&
1673 Base.getOpcode() != ISD::Register) {
1681 if (Index.getOpcode() != ISD::Register) {
1704 if (N.getOpcode() == ISD::LOAD && U->getOpcode() == SystemZISD::ICMP) {
lib/Target/SystemZ/SystemZISelLowering.cpp 1983 C.Op0.getOpcode() != ISD::LOAD ||
1984 C.Op1.getOpcode() != ISD::Constant)
2116 unsigned Opcode0 = C.Op0.getOpcode();
2123 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
2185 if (C.Op0.getOpcode() == ISD::SHL &&
2187 C.Op1.getOpcode() == ISD::Constant &&
2210 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
2211 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
2212 C.Op1.getOpcode() == ISD::Constant &&
2351 if (C.Op0.getOpcode() == ISD::AND) {
2388 NewC.Op0.getOpcode() == ISD::SHL &&
2399 NewC.Op0.getOpcode() == ISD::SRL &&
2432 if (C.Op0.getOpcode() != ISD::AND)
2483 if (CmpOp1.getOpcode() == ISD::Constant) {
2486 if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
2490 if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2539 switch (C.Op0.getOpcode()) {
2769 return (Neg.getOpcode() == ISD::SUB &&
2770 Neg.getOperand(0).getOpcode() == ISD::Constant &&
2774 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
2805 C.Op1.getOpcode() == ISD::Constant &&
3404 if (HighOp.getOpcode() == ISD::Constant)
3409 if (LowOp.getOpcode() == ISD::Constant) {
3417 if (HighOp.getOpcode() == ISD::AND &&
3418 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
3446 switch (Op.getOpcode()) {
3481 while (Carry.getOpcode() == ISD::ADDCARRY)
3483 return Carry.getOpcode() == ISD::UADDO;
3487 while (Carry.getOpcode() == ISD::SUBCARRY)
3489 return Carry.getOpcode() == ISD::USUBO;
3511 switch (Op.getOpcode()) {
4165 if (SystemZISD::SPLAT == ShuffleOp.getOpcode() &&
4338 if (Op.getOpcode() == ISD::BITCAST)
4340 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
4471 if (Value.getOpcode() == ISD::Constant ||
4472 Value.getOpcode() == ISD::ConstantFP) {
4534 if (Op.getOpcode() == ISD::TRUNCATE)
4536 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4537 Op.getOperand(1).getOpcode() == ISD::Constant) {
4570 if (Op.getOpcode() == ISD::LOAD && cast<LoadSDNode>(Op)->isUnindexed())
4572 if (Subtarget.hasVectorEnhancements2() && Op.getOpcode() == SystemZISD::LRV)
4644 if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
4660 if (Elem.getOpcode() == ISD::Constant ||
4661 Elem.getOpcode() == ISD::ConstantFP) {
4765 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4766 Op0.getOpcode() == ISD::BUILD_VECTOR)
4807 Op1.getOpcode() != ISD::BITCAST &&
4808 Op1.getOpcode() != ISD::ConstantFP &&
4809 Op2.getOpcode() == ISD::Constant) {
4910 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4911 VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
4927 switch (Op.getOpcode()) {
5277 unsigned Opcode = Op.getOpcode();
5377 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5413 if (N0.getOpcode() == SystemZISD::SELECT_CCMASK) {
5443 if (N0.hasOneUse() && N0.getOpcode() == ISD::ANY_EXTEND)
5445 if (EVT == MVT::i1 && N0.hasOneUse() && N0.getOpcode() == ISD::SETCC) {
5463 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
5466 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
5491 if (Op0.getOpcode() == ISD::BITCAST)
5607 Op1.getOpcode() == ISD::BSWAP &&
5626 Op1.getOpcode() == ISD::VECTOR_SHUFFLE &&
5693 if (Op.getOpcode() == ISD::BITCAST &&
5701 if (Op.getOpcode() == ISD::BSWAP && Op.hasOneUse()) {
5751 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5753 Op0.getOperand(1).getOpcode() == ISD::Constant &&
5761 U->getOperand(1).getOpcode() == ISD::Constant &&
5764 if (OtherRound.getOpcode() == ISD::FP_ROUND &&
5802 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5804 Op0.getOperand(1).getOpcode() == ISD::Constant &&
5812 U->getOperand(1).getOpcode() == ISD::Constant &&
5815 if (OtherExtend.getOpcode() == ISD::FP_EXTEND &&
5879 if (Op.getOpcode() == ISD::BITCAST &&
5887 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) {
5893 Vec.getOpcode() == ISD::BSWAP || Vec.isUndef() ||
5895 Elt.getOpcode() == ISD::BSWAP || Elt.isUndef() ||
5924 Op0.getOpcode() == ISD::BSWAP || Op0.isUndef() ||
5926 Op1.getOpcode() == ISD::BSWAP || Op1.isUndef()) {
6190 unsigned Opcode = Op.getOpcode();
6319 unsigned Opcode = Op.getOpcode();
6420 unsigned Opcode = Op.getOpcode();
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 975 switch (Op.getOpcode()) {
1201 switch (Op.getOpcode()) {
1261 if (Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1309 return V.getOpcode() == ISD::Constant || V.getOpcode() == ISD::ConstantFP;
1309 return V.getOpcode() == ISD::Constant || V.getOpcode() == ISD::ConstantFP;
1504 DAG.getNode(Op.getOpcode(), // original shift opcode
1533 switch (Op.getOpcode()) {
lib/Target/X86/X86ISelDAGToDAG.cpp 578 if (N.getOpcode() != ISD::LOAD)
653 if (Op1.getOpcode() == X86ISD::Wrapper) {
655 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
664 if (U->getOperand(0).getOpcode() == ISD::SHL &&
668 if (U->getOperand(1).getOpcode() == ISD::SHL &&
675 if (U0.getOpcode() == ISD::ROTL) {
681 if (U1.getOpcode() == ISD::ROTL) {
724 assert(Chain.getOpcode() == ISD::TokenFactor &&
767 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
782 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
1410 bool IsRIPRel = N.getOpcode() == X86ISD::WrapperRIP;
1413 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
1570 if (Shift.getOpcode() != ISD::SRL ||
1623 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() &&
1630 if (Shift.getOpcode() != ISD::SHL ||
1706 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
1739 if (X.getOpcode() == ISD::ANY_EXTEND) {
1794 if (Shift.getOpcode() != ISD::SRL ||
1872 switch (N.getOpcode()) {
1952 if (And.getOpcode() != ISD::AND) break;
2107 if (N.getOperand(0).getOpcode() == ISD::SRL) {
2138 if (N.getOperand(0).getOpcode() != ISD::SHL || !N.getOperand(0).hasOneUse())
2202 switch (N.getOpcode()) {
2332 if (N.getOpcode() == X86ISD::VZEXT_LOAD) {
2345 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR && N.getNode()->hasOneUse()) {
2481 if (N.getOpcode() == ISD::ADD) {
2483 switch (V.getOpcode()) {
2524 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
2554 if (N.getOpcode() == ISD::TRUNCATE) {
2559 if (N.getOpcode() != X86ISD::Wrapper)
2887 } else if (Chain.getOpcode() == ISD::TokenFactor) {
3254 if (Mask.getOpcode() != ISD::XOR || !checkOneUse(Mask))
3274 if (ShiftAmt.getOpcode() == ISD::TRUNCATE) {
3281 if (ShiftAmt.getOpcode() != ISD::SUB)
3297 if (Mask.getOpcode() != ISD::SRL || !checkOneUse(Mask))
3391 if (RealX != X && RealX.getOpcode() == ISD::SRL)
3411 if (X.getOpcode() == ISD::SRL) {
3742 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() &&
3749 if (Shift.getOpcode() != ISD::SHL || !Shift.hasOneUse())
4144 if (N0Temp.getOpcode() == ISD::BITCAST && N0Temp.hasOneUse())
4148 if (N0Temp.getOpcode() == ISD::AND && N0Temp.hasOneUse()) {
4179 if (Src.getOpcode() == ISD::BITCAST && Src.hasOneUse()) {
4184 if (Src.getOpcode() == X86ISD::VBROADCAST_LOAD && Src.hasOneUse()) {
4319 if (N1.getOpcode() == ISD::AND)
4322 if (N0.getOpcode() != ISD::AND ||
4323 N1.getOpcode() != X86ISD::ANDNP ||
4483 if (N0.getOpcode() == ISD::SETCC && N0.hasOneUse() &&
4486 if (N1.getOpcode() == ISD::SETCC && N1.hasOneUse() &&
4986 if (N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
4999 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse())
5005 if (N0.getOpcode() == ISD::AND &&
lib/Target/X86/X86ISelLowering.cpp 4215 unsigned Op = Arg.getOpcode();
4222 if (TruncInput.getOpcode() == ISD::AssertZext &&
4233 if (Arg.getOpcode() == ISD::CopyFromReg) {
4266 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
4867 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4973 unsigned Opc = VecOp.getOpcode();
5116 N->getOperand(0).getOpcode() == ISD::SRL) ||
5118 N->getOperand(0).getOpcode() == ISD::SHL)) &&
5475 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
5589 Src.getOpcode() == ISD::INSERT_SUBVECTOR &&
5868 if (V.getOpcode() == ISD::XOR &&
5871 if (V.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
6122 if (Op.getOpcode() == X86ISD::VBROADCAST &&
6139 if (Op.getOpcode() == X86ISD::VBROADCAST_LOAD &&
6171 if (Op.getOpcode() == X86ISD::SUBV_BROADCAST) {
6184 if (Op.getOpcode() == X86ISD::VZEXT_MOVL &&
6185 Op.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6199 if (Op.getOpcode() == ISD::INSERT_SUBVECTOR &&
6222 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
6554 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
6729 if (!isTargetShuffle(N.getOpcode()))
6785 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6868 unsigned Opcode = N.getOpcode();
6985 if (Sub.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
7045 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7047 (N0.getOpcode() == X86ISD::PEXTRW &&
7049 (N0.getOpcode() == X86ISD::PEXTRB &&
7094 if (InScl.getOpcode() != ExOp)
7327 unsigned Opcode = V.getOpcode();
7399 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7403 if (V.getOpcode() == ISD::BUILD_VECTOR)
7570 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7753 switch (Elt.getOpcode()) {
8184 if ((ZeroExtended && ZeroExtended.getOpcode() == ISD::BITCAST) ||
8185 (Ld && Ld.getOpcode() == ISD::ZERO_EXTEND &&
8186 Ld.getOperand(0).getOpcode() == ISD::BITCAST)) {
8294 (Ld.getOpcode() == ISD::Constant || Ld.getOpcode() == ISD::ConstantFP);
8294 (Ld.getOpcode() == ISD::Constant || Ld.getOpcode() == ISD::ConstantFP);
8426 unsigned Opc = Op.getOperand(i).getOpcode();
8537 if (Cond.getOpcode() != ISD::SETCC)
8634 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
8635 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
8774 unsigned Opcode = Op.getOpcode();
8788 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8789 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8881 if (Opnd0.getOpcode() != ISD::FMUL ||
8964 if (HOpcode != ISD::DELETED_NODE && Op.getOpcode() != GenericOpcode)
8969 GenericOpcode = Op.getOpcode();
8981 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8982 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
9195 unsigned Opcode = Op->getOperand(0).getOpcode();
9197 if (Opcode != Op->getOperand(i).getOpcode())
9546 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9558 if (ExtractedIndex.getOpcode() == ISD::ZERO_EXTEND ||
9559 ExtractedIndex.getOpcode() == ISD::SIGN_EXTEND)
9561 if (ExtractedIndex.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10461 if (V.getOpcode() != ISD::BUILD_VECTOR)
10796 if (V1.getOpcode() != ISD::BITCAST)
10798 if (V1.getOperand(0).getOpcode() != ISD::TRUNCATE)
12237 if (V.getOpcode() == ISD::BUILD_VECTOR ||
12238 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
12387 const unsigned V0Opc = V0.getOpcode();
12444 N0.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
12445 N1.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
12528 switch (V.getOpcode()) {
12582 ((V.getOpcode() == ISD::BUILD_VECTOR && V.hasOneUse()) ||
12583 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0))) {
18234 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
18248 if (Op.getOpcode() == ISD::SHL_PARTS) {
18265 if (Op.getOpcode() == ISD::SHL_PARTS) {
18279 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) &&
18279 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) &&
18287 bool IsFSHR = Op.getOpcode() == ISD::FSHR;
18330 assert((Op.getOpcode() == ISD::SINT_TO_FP ||
18331 Op.getOpcode() == ISD::UINT_TO_FP) && "Unexpected opcode!");
18349 SDValue CvtVec = DAG.getNode(Op.getOpcode(), dl, VecVT, InVec);
18385 if (Extract.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
18395 if (!useVectorCast(Cast.getOpcode(), Vec128VT, ToVT, Subtarget))
18413 SDValue VCast = DAG.getNode(Cast.getOpcode(), DL, ToVT, VecOp);
19034 unsigned Opc = Op.getOpcode();
19515 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT;
19523 if (Op.getOpcode() == ISD::FP_TO_SINT)
19670 if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
19671 RHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
19681 switch (Op.getOpcode()) {
19728 RTLIB::Libcall LC = Op.getOpcode() == ISD::FADD ? RTLIB::ADD_F128
19741 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
19741 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
19744 bool IsFABS = (Op.getOpcode() == ISD::FABS);
19783 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
19902 assert(Op.getOpcode() == unsigned(BinOp) &&
19910 if (I->getOpcode() == unsigned(BinOp)) {
19919 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
19962 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
20067 switch (ArithOp.getOpcode()) {
20090 switch (ArithOp.getOpcode()) {
20161 if (Op0.getOpcode() == ISD::TRUNCATE) {
20167 } else if (Op1.getOpcode() == ISD::TRUNCATE) {
20193 Cmp.getOpcode() != X86ISD::CMP ||
20366 assert(And.getOpcode() == ISD::AND && "Expected AND node!");
20369 if (Op0.getOpcode() == ISD::TRUNCATE)
20371 if (Op1.getOpcode() == ISD::TRUNCATE)
20375 if (Op1.getOpcode() == ISD::SHL)
20377 if (Op0.getOpcode() == ISD::SHL) {
20391 } else if (Op1.getOpcode() == ISD::Constant) {
20396 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
20492 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
20513 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
20514 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
20744 if (BC0.getOpcode() == ISD::AND) {
20759 if (Cond == ISD::SETEQ && Op0.getOpcode() == ISD::AND &&
20952 if (Op0.getOpcode() != ISD::BITCAST)
20979 if (KTestable && Op0.getOpcode() == ISD::AND && Op0.hasOneUse()) {
20989 if (Op0.getOpcode() == ISD::OR && Op0.hasOneUse()) {
21008 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && isNullConstant(Op1) &&
21016 if (Op0.getOpcode() == ISD::OR && isNullConstant(Op1) &&
21032 if (Op0.getOpcode() == X86ISD::SETCC) {
21123 switch (Op.getOpcode()) {
21178 unsigned Opc = Op.getOpcode();
21192 if (V.getOpcode() != ISD::TRUNCATE)
21213 if (Cond.getOpcode() == ISD::SETCC &&
21290 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
21295 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
21308 if (Cond.getOpcode() == ISD::SETCC) {
21325 if (Cond.getOpcode() == X86ISD::SETCC &&
21326 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
21364 Cmp.getOperand(0).getOpcode() == ISD::AND &&
21372 if ((Op2.getOpcode() == ISD::XOR || Op2.getOpcode() == ISD::OR) &&
21372 if ((Op2.getOpcode() == ISD::XOR || Op2.getOpcode() == ISD::OR) &&
21398 return DAG.getNode(Op2.getOpcode(), DL, VT, And, Src2); // And Op y
21404 if (Cond.getOpcode() == ISD::AND &&
21405 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
21411 unsigned CondOpcode = Cond.getOpcode();
21423 Cmp.getOpcode() == X86ISD::BT) { // FIXME
21445 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
21465 if (Cond.getOpcode() == X86ISD::SUB) {
21485 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
21485 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
21489 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
21489 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
21535 return SplitAndExtendv16i1(Op.getOpcode(), VT, In, dl, DAG);
21554 V = DAG.getNode(Op.getOpcode(), dl, WideVT, In);
21612 unsigned Opc = Op.getOpcode();
21632 return DAG.getNode(Op.getOpcode(), dl, VT, In);
21945 Opc = Op.getOpcode();
21948 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
21950 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
21957 if (Op.getOpcode() != ISD::XOR)
21960 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
21974 if (Cond.getOpcode() == ISD::SETCC) {
21979 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
21980 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
21981 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
21982 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
21983 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
21984 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
22002 if (Cond.getOpcode() == ISD::AND &&
22003 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
22009 unsigned CondOpcode = Cond.getOpcode();
22015 unsigned Opc = Cmp.getOpcode();
22033 CondOpcode = Cond.getOpcode();
22109 } else if (Cond.getOpcode() == ISD::SETCC &&
22140 } else if (Cond.getOpcode() == ISD::SETCC &&
22164 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
22544 else if (ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
22545 ShAmt.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
22564 ShAmt.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
22666 if (Op.getOpcode() == X86ISD::FSETCCM ||
22667 Op.getOpcode() == X86ISD::FSETCCM_SAE ||
22668 Op.getOpcode() == X86ISD::VFPCLASSS)
24603 DAG.getNode(Op.getOpcode(), dl, NewVT, Lo),
24604 DAG.getNode(Op.getOpcode(), dl, NewVT, Hi));
24631 assert(Op.getOpcode() == ISD::CTLZ);
24769 unsigned Opc = Op.getOpcode();
24809 assert(!VT.isVector() && Op.getOpcode() == ISD::CTTZ &&
24848 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
24849 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
24877 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
24878 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
24901 unsigned Opcode = Op.getOpcode();
24987 unsigned Opcode = Op.getOpcode();
25492 unsigned X86Opc = getTargetVShiftUniformOpcode(Op.getOpcode(), false);
25544 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
25550 Op.getOpcode() == ISD::SRA)
25559 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
25563 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
25577 if (Op.getOpcode() == ISD::SHL) {
25586 if (Op.getOpcode() == ISD::SRL) {
25595 if (Op.getOpcode() == ISD::SRA) {
25616 unsigned Opcode = Op.getOpcode();
25678 if (VT == MVT::v2i64 && Amt.getOpcode() == ISD::BITCAST &&
25679 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
25691 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
25770 unsigned Opc = Op.getOpcode();
26250 unsigned Opcode = Op.getOpcode();
27268 unsigned Opc = Op.getOpcode() == ISD::ADDCARRY ? X86ISD::ADC : X86ISD::SBB;
27354 if (InOp.getOpcode() == ISD::CONCAT_VECTORS &&
27661 switch (Op.getOpcode()) {
29070 if (Val.getOpcode() != ISD::LOAD)
31428 if (Op.getOpcode() != ISD::AND)
31487 unsigned Opc = Op.getOpcode();
31672 unsigned Opcode = Op.getOpcode();
32343 if (Src.getOpcode() == ISD::INSERT_SUBVECTOR &&
32363 if (Depth == 0 && Root.getOpcode() == X86ISD::VPERM2X128)
32422 if (V1.getOpcode() == X86ISD::VZEXT_LOAD &&
32442 V1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
32444 if (Depth == 0 && Root.getOpcode() == X86ISD::VBROADCAST)
32451 if (Depth == 0 && Root.getOpcode() == X86ISD::VBROADCAST)
32465 if (Depth == 0 && Root.getOpcode() == Shuffle)
32476 if (Depth == 0 && Root.getOpcode() == Shuffle)
32491 if (Depth == 0 && Root.getOpcode() == Shuffle)
32505 if (Depth == 0 && Root.getOpcode() == Shuffle)
32523 if (Depth == 0 && Root.getOpcode() == X86ISD::EXTRQI)
32533 if (Depth == 0 && Root.getOpcode() == X86ISD::INSERTQI)
32832 while (Src.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
33057 bool IsOpVariableMask = isTargetShuffleVariableMask(Op.getOpcode());
33277 switch (N.getOpcode()) {
33301 assert(N.getOpcode() == X86ISD::PSHUFD &&
33311 switch (V.getOpcode()) {
33354 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
33361 switch (V.getOpcode()) {
33367 if (V.getOpcode() == CombineOp)
33393 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
33403 switch (W.getOpcode()) {
33409 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
33415 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
33433 unsigned Opcode = N.getOpcode();
33444 unsigned Opcode0 = BC0.getOpcode();
33445 unsigned Opcode1 = BC1.getOpcode();
33472 if (isTargetShuffle(BC.getOpcode()) &&
33488 if (Src.getOpcode() == ISD::BITCAST &&
33501 if (Src.getOpcode() == ISD::SCALAR_TO_VECTOR)
33544 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
33544 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
33567 if (N0.getOpcode() == ISD::BITCAST &&
33590 unsigned Opcode1 = N1.getOpcode();
33700 if (Op1.getOpcode() == X86ISD::VBROADCAST_LOAD && Op1.hasOneUse()) {
33727 switch (N.getOpcode()) {
33739 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
33753 (V.getOpcode() == X86ISD::PSHUFLW ||
33754 V.getOpcode() == X86ISD::PSHUFHW) &&
33755 V.getOpcode() != N.getOpcode() &&
33755 V.getOpcode() != N.getOpcode() &&
33758 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
33761 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
33762 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
33855 if ((V1.getOpcode() != ISD::FADD && V1.getOpcode() != ISD::FSUB) ||
33855 if ((V1.getOpcode() != ISD::FADD && V1.getOpcode() != ISD::FSUB) ||
33856 (V2.getOpcode() != ISD::FADD && V2.getOpcode() != ISD::FSUB) ||
33856 (V2.getOpcode() != ISD::FADD && V2.getOpcode() != ISD::FSUB) ||
33857 V1.getOpcode() == V2.getOpcode())
33857 V1.getOpcode() == V2.getOpcode())
33867 if (V1.getOpcode() == ISD::FSUB) {
33873 assert(V2.getOpcode() == ISD::FSUB && "Unexpected opcode");
33913 if (FMSub.getOpcode() != X86ISD::FMSUB)
33916 if (FMAdd.getOpcode() != ISD::FMA || FMSub.getOpcode() != X86ISD::FMSUB ||
33916 if (FMAdd.getOpcode() != ISD::FMA || FMSub.getOpcode() != X86ISD::FMSUB ||
33995 if (N0.getOpcode() != ISD::CONCAT_VECTORS ||
33996 N1.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 ||
34028 if (SrcOp.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
34036 if (HOp.getOpcode() != X86ISD::HADD && HOp.getOpcode() != X86ISD::FHADD &&
34036 if (HOp.getOpcode() != X86ISD::HADD && HOp.getOpcode() != X86ISD::FHADD &&
34037 HOp.getOpcode() != X86ISD::HSUB && HOp.getOpcode() != X86ISD::FHSUB)
34037 HOp.getOpcode() != X86ISD::HSUB && HOp.getOpcode() != X86ISD::FHSUB)
34063 return DAG.getNode(HorizOp.getOpcode(), SDLoc(HorizOp),
34195 N->getOperand(0).getOpcode() == ISD::BITCAST &&
34199 switch (In.getOpcode()) {
34221 N->getOperand(0).getOpcode() == ISD::INSERT_SUBVECTOR &&
34258 unsigned Opc = Op.getOpcode();
34327 if (Src.getOpcode() == X86ISD::KSHIFTR) {
34366 if (Src.getOpcode() == X86ISD::KSHIFTL) {
34713 unsigned Opc = Op.getOpcode();
34757 if (Op0.getOpcode() == X86ISD::VSRLI &&
34824 if (Op0.getOpcode() == X86ISD::VSHLI && Op1 == Op0.getOperand(1)) {
34996 unsigned Opc = Op.getOpcode();
35090 if (!isTargetShuffle(InVec.getOpcode()))
35135 if (LdNode.getOpcode() == ISD::BITCAST) {
35179 switch (Src.getOpcode()) {
35194 switch (Src.getOpcode()) {
35201 Src.getOpcode(), DL, SExtVT,
35225 bool IsTruncated = Src.getOpcode() == ISD::TRUNCATE && Src.hasOneUse() &&
35351 if (Op.getOpcode() != ISD::AND &&
35352 Op.getOpcode() != ISD::OR &&
35353 Op.getOpcode() != ISD::XOR)
35366 if (LHS.hasOneUse() && LHS.getOpcode() == ISD::BITCAST &&
35368 return DAG.getNode(Op.getOpcode(), SDLoc(N), DstVT, LHS.getOperand(0),
35371 if (RHS.hasOneUse() && RHS.getOpcode() == ISD::BITCAST &&
35373 return DAG.getNode(Op.getOpcode(), SDLoc(N), DstVT,
35380 return DAG.getNode(Op.getOpcode(), SDLoc(N), DstVT,
35479 VT.isScalarInteger() && N0.getOpcode() == ISD::SETCC &&
35486 (N00.getOpcode() == ISD::BITCAST &&
35515 if (N0.getOpcode() == ISD::CONCAT_VECTORS) {
35543 !Subtarget.hasDQI() && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
35551 if (N0.getOpcode() == X86ISD::VBROADCAST_LOAD && N0.hasOneUse() &&
35584 if (N0.getOpcode() == ISD::BUILD_VECTOR &&
35605 if (N0.getOpcode() == ISD::BUILD_VECTOR &&
35611 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
35612 N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) &&
35621 if (SrcVT == MVT::v2i32 && N0.getOpcode() == ISD::FP_TO_SINT) {
35659 switch (N0.getOpcode()) {
35675 if (N0.hasOneUse() && LogicOp0.getOpcode() == ISD::BITCAST &&
35682 if (N0.hasOneUse() && LogicOp1.getOpcode() == ISD::BITCAST &&
35697 if (AbsOp1.getOpcode() != ISD::SUB)
35704 if (Op0.getOpcode() != ISD::ZERO_EXTEND ||
35706 Op1.getOpcode() != ISD::ZERO_EXTEND ||
35987 if (Root && (Root.getOpcode() == ISD::SIGN_EXTEND ||
35988 Root.getOpcode() == ISD::ZERO_EXTEND ||
35989 Root.getOpcode() == ISD::ANY_EXTEND))
35994 if (!Root || Root.getOpcode() != ISD::ABS)
36057 if (X86ISD::VBROADCAST == SrcBC.getOpcode()) {
36065 if (SrcBC.getOpcode() == X86ISD::VBROADCAST_LOAD && SrcBC.hasOneUse()) {
36083 if (ISD::TRUNCATE == Src.getOpcode() && SrcVT.is128BitVector() &&
36181 if (Vec.getOpcode() == ISD::SETCC && VT == MVT::i1) {
36192 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1, Vec.getOperand(2));
36204 if (Vec.getOpcode() == ISD::VSELECT &&
36205 Vec.getOperand(0).getOpcode() == ISD::SETCC &&
36223 switch (Vec.getOpcode()) {
36255 return DAG.getNode(Vec.getOpcode(), DL, VT, ExtOps);
36418 if ((InputVector.getOpcode() == X86ISD::PINSRB ||
36419 InputVector.getOpcode() == X86ISD::PINSRW) &&
36438 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
36448 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
36570 Cond.getOpcode() == ISD::SETCC &&
36835 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
36990 Cond.getOpcode() == ISD::SETCC && (VT == MVT::f32 || VT == MVT::f64)) {
36993 if (AndNode.getOpcode() == ISD::AND && CC == ISD::SETEQ &&
37025 return Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
37026 isTargetShuffle(Op.getOperand(0).getOpcode()) &&
37072 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
37090 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
37144 if (CC == ISD::SETLT && Other.getOpcode() == ISD::XOR &&
37159 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
37180 if (Other.getNode() && Other.getOpcode() == ISD::ADD) {
37251 if (!(Cmp.getOpcode() == X86ISD::CMP ||
37252 (Cmp.getOpcode() == X86ISD::SUB && !Cmp->hasAnyUseOfValue(0))))
37279 unsigned Opc = CmpLHS.getOpcode();
37356 if (!(Cmp.getOpcode() == X86ISD::CMP ||
37357 (Cmp.getOpcode() == X86ISD::SUB && !Cmp->hasAnyUseOfValue(0))))
37390 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
37391 SetCC.getOpcode() == ISD::TRUNCATE ||
37392 SetCC.getOpcode() == ISD::AND) {
37393 if (SetCC.getOpcode() == ISD::AND) {
37407 switch (SetCC.getOpcode()) {
37435 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
37436 Op.getOpcode() == ISD::TRUNCATE)
37440 if ((Op.getOpcode() != X86ISD::RDRAND &&
37441 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
37499 if (SetCC0.getOpcode() != X86ISD::SETCC ||
37500 SetCC1.getOpcode() != X86ISD::SETCC ||
37514 if (EFLAGS.getOpcode() == X86ISD::ADD) {
37517 while (Carry.getOpcode() == ISD::TRUNCATE ||
37518 Carry.getOpcode() == ISD::ZERO_EXTEND ||
37519 Carry.getOpcode() == ISD::SIGN_EXTEND ||
37520 Carry.getOpcode() == ISD::ANY_EXTEND ||
37521 (Carry.getOpcode() == ISD::AND &&
37524 if (Carry.getOpcode() == X86ISD::SETCC ||
37525 Carry.getOpcode() == X86ISD::SETCC_CARRY) {
37538 if (CarryOp1.getOpcode() == X86ISD::SUB &&
37551 CarryOp1.getOpcode() == X86ISD::ADD &&
37704 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
37704 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
37766 Cond.getOpcode() == X86ISD::CMP && isNullConstant(Cond.getOperand(1))) {
37779 if (isa<ConstantSDNode>(Const) && Add.getOpcode() == ISD::ADD &&
37781 (Add.getOperand(0).getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
37782 Add.getOperand(0).getOpcode() == ISD::CTTZ) &&
38044 (N0.getOpcode() == ISD::ZERO_EXTEND &&
38046 (N1.getOpcode() == ISD::ZERO_EXTEND &&
38261 N1C && N0.getOpcode() == ISD::AND &&
38262 N0.getOperand(1).getOpcode() == ISD::Constant) {
38278 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
38280 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
38281 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
38283 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
38284 N00.getOpcode() == ISD::ANY_EXTEND) &&
38285 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
38328 if (VT.isVector() || N1.getOpcode() != ISD::Constant ||
38329 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
38330 N0.getOperand(1).getOpcode() != ISD::Constant)
38379 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
38489 N0.getOpcode() == ISD::TRUNCATE && N1.isUndef() && VT == MVT::v16i8 &&
38582 if (Opcode == X86ISD::VSRAI && N0.getOpcode() == X86ISD::VSRAI) {
38664 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
38805 if (N0.getOpcode() != ISD::TRUNCATE)
38813 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE &&
38856 if (N0.getOpcode() != ISD::BITCAST || N1.getOpcode() != ISD::BITCAST)
38856 if (N0.getOpcode() != ISD::BITCAST || N1.getOpcode() != ISD::BITCAST)
38926 if (Base.getOpcode() != ISD::ADD)
38931 if (ShiftedIndex.getOpcode() != ISD::SHL)
39056 if (N0.getOpcode() != ISD::CTPOP || !N0.hasOneUse())
39124 if (N->getOperand(0).getOpcode() != ISD::BITCAST ||
39136 if (Src.getOpcode() != ISD::CONCAT_VECTORS)
39146 if (SubVec.getOpcode() != ISD::SETCC || !TLI.isTypeLegal(SubVecVT) ||
39248 N->getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
39299 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
39299 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
39345 if (N1.getOpcode() == ISD::AND)
39349 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != X86ISD::ANDNP)
39349 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != X86ISD::ANDNP)
39532 N->getOperand(1).getOpcode() == X86ISD::CMP &&
39660 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
39660 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
39662 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
39662 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
39676 if (ShAmt0.getOpcode() == ISD::AND &&
39683 if (ShAmt1.getOpcode() == ISD::AND &&
39690 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
39692 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
39699 if (ShAmt0.getOpcode() == ISD::SUB || ShAmt0.getOpcode() == ISD::XOR) {
39699 if (ShAmt0.getOpcode() == ISD::SUB || ShAmt0.getOpcode() == ISD::XOR) {
39720 if (ShAmt1.getOpcode() == ISD::SUB) {
39724 if (ShAmt1Op1.getOpcode() == ISD::AND &&
39730 if (ShAmt1Op1.getOpcode() == ISD::TRUNCATE)
39741 } else if (ShAmt1.getOpcode() == ISD::XOR) {
39746 if (ShAmt1Op0.getOpcode() == ISD::TRUNCATE)
39750 if (Op1.getOpcode() == InnerShift &&
39756 if (InnerShift == ISD::SHL && Op1.getOpcode() == ISD::ADD &&
39781 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
39790 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
39848 if (Shift.getOpcode() != ISD::SRA || !Shift.hasOneUse() ||
39890 if (V.getOpcode() == Opcode &&
39935 if (V.getOpcode() == Opcode &&
40098 if (In.getOpcode() != ISD::SRL)
40123 if (LHS.getOpcode() != ISD::ADD)
40139 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
40154 if (ISD::ADD == V.getOpcode()) {
40159 if (ISD::ZERO_EXTEND != V.getOpcode())
40162 if (V.getValueType() != VT || ISD::OR != V.getOpcode() ||
40188 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
40477 if (Value.getOpcode() == ISD::TRUNCATE && Value.getNode()->hasOneUse() &&
40514 StoredVal.getOpcode() == ISD::SCALAR_TO_VECTOR &&
40604 St->getValue().getOpcode() == ISD::TRUNCATE &&
40615 (StoredVal.getOpcode() == X86ISD::VTRUNCUS ||
40616 StoredVal.getOpcode() == X86ISD::VTRUNCS) &&
40618 bool IsSigned = StoredVal.getOpcode() == X86ISD::VTRUNCS;
40733 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
40786 if (Op.getOpcode() == ISD::VECTOR_SHUFFLE) {
40796 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
40806 if (isTargetShuffle(BC.getOpcode()) &&
40941 unsigned SrcOpcode = Src.getOpcode();
40952 unsigned Opcode = Op.getOpcode();
41172 if (Src.getOpcode() != ISD::SRL ||
41173 Src.getOperand(0).getOpcode() != ISD::MUL)
41198 unsigned ExtOpc = LHS.getOpcode();
41200 RHS.getOpcode() != ExtOpc)
41235 if (!SSatVal || SSatVal.getOpcode() != ISD::ADD)
41243 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL)
41243 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL)
41253 if (N01.getOpcode() == ISD::ZERO_EXTEND)
41255 if (N11.getOpcode() == ISD::ZERO_EXTEND)
41259 if (N00.getOpcode() != ISD::ZERO_EXTEND ||
41260 N01.getOpcode() != ISD::SIGN_EXTEND ||
41261 N10.getOpcode() != ISD::ZERO_EXTEND ||
41262 N11.getOpcode() != ISD::SIGN_EXTEND)
41279 if (N00.getOpcode() != ISD::BUILD_VECTOR ||
41280 N01.getOpcode() != ISD::BUILD_VECTOR ||
41281 N10.getOpcode() != ISD::BUILD_VECTOR ||
41282 N11.getOpcode() != ISD::BUILD_VECTOR)
41300 if (N00Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
41301 N01Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
41302 N10Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
41303 N11Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
41382 if (Src.getOpcode() == ISD::BITCAST && VT == MVT::i32) {
41444 unsigned Opc = Op.getOpcode();
41559 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
41570 switch (Arg.getOpcode()) {
41582 unsigned NewOpcode = negateFMAOpcode(Arg.getOpcode(), false, false, true);
41605 switch (Op.getOpcode()) {
41644 unsigned Opc = Op.getOpcode();
41831 if (N0.getOpcode() == X86ISD::FXOR && isAllOnesConstantFP(N0.getOperand(1)))
41835 if (N1.getOpcode() == X86ISD::FXOR && isAllOnesConstantFP(N1.getOperand(1)))
42112 if ((N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
42112 if ((N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
42119 if (N0.getOpcode() != X86ISD::CMOV || !N0.hasOneUse())
42134 unsigned IntermediateOpc = IntermediateBitwidthOp.getOpcode();
42177 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
42178 N0.getOpcode() == ISD::SIGN_EXTEND)) {
42183 if (N00.getOpcode() == ISD::LOAD && Subtarget.hasInt256())
42213 if (Add.getOpcode() != ISD::ADD)
42275 if (CMovN.getOpcode() != X86ISD::CMOV || !CMovN.hasOneUse())
42345 if (InSVT != MVT::i1 || N0.getOpcode() != ISD::BITCAST)
42416 if (!Subtarget.hasAVX512() || !VT.isVector() || N0.getOpcode() != ISD::SETCC)
42467 if (InVT == MVT::i1 && N0.getOpcode() == ISD::XOR &&
42518 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
42585 if (N0.getOpcode() == ISD::AND &&
42589 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
42599 if (N0.getOpcode() == ISD::TRUNCATE &&
42603 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
42632 if (N0.getOpcode() == X86ISD::PACKUS && N0.getValueSizeInBits() == 128 &&
42667 bool IsOrXorXorCCZero = isNullConstant(Y) && X.getOpcode() == ISD::OR &&
42668 X.getOperand(0).getOpcode() == ISD::XOR &&
42669 X.getOperand(1).getOpcode() == ISD::XOR;
42677 X.getOpcode() == ISD::LOAD;
42727 if (X.getOpcode() == ISD::ZERO_EXTEND) {
42827 if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
42834 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
42847 if (LHS.getOpcode() == ISD::BUILD_VECTOR) {
42853 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
42919 if (Subtarget.hasSSE2() && Src.getOpcode() == ISD::BITCAST &&
43004 if ((Index.getOpcode() == ISD::SIGN_EXTEND ||
43005 Index.getOpcode() == ISD::ZERO_EXTEND) &&
43154 if (!Trunc.hasOneUse() || Trunc.getOpcode() != ISD::TRUNCATE)
43158 if (!ExtElt.hasOneUse() || ExtElt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
43262 Op0.getOpcode() == ISD::LOAD) {
43371 if ((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) &&
43371 if ((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) &&
43378 APInt Mask = Op.getOpcode() == ISD::SRL
43391 if (Op.getOpcode() != ISD::TRUNCATE || !Op.hasOneUse())
43401 switch (Op.getOpcode()) {
43490 if (Op0.getOpcode() == ISD::SUB && isNullConstant(Op1) &&
43542 if (!IsSub && X.getOpcode() == ISD::ZERO_EXTEND &&
43543 Y.getOpcode() != ISD::ZERO_EXTEND)
43548 if (Y.getOpcode() == ISD::ZERO_EXTEND && Y.hasOneUse()) {
43556 if (!IsSub && !PeekedThroughZext && X.getOpcode() == X86ISD::SETCC &&
43557 Y.getOpcode() != X86ISD::SETCC)
43560 if (Y.getOpcode() != X86ISD::SETCC || !Y.hasOneUse())
43584 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
43617 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.getNode()->hasOneUse() &&
43634 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
43708 return Op.getOpcode() == ISD::MUL &&
43784 if (AbsOp.getOpcode() != ISD::ABS)
43786 if (AbsOp.getOpcode() != ISD::ABS)
43846 if (Op0.getOpcode() != ISD::BUILD_VECTOR ||
43847 Op1.getOpcode() != ISD::BUILD_VECTOR)
43871 if (Op0L.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
43872 Op1L.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
43873 Op0H.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
43874 Op1H.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
43947 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL)
43947 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL)
43962 if (N00.getOpcode() != ISD::SIGN_EXTEND ||
43963 N01.getOpcode() != ISD::SIGN_EXTEND ||
43964 N10.getOpcode() != ISD::SIGN_EXTEND ||
43965 N11.getOpcode() != ISD::SIGN_EXTEND)
43981 if (N00.getOpcode() != ISD::BUILD_VECTOR ||
43982 N01.getOpcode() != ISD::BUILD_VECTOR ||
43983 N10.getOpcode() != ISD::BUILD_VECTOR ||
43984 N11.getOpcode() != ISD::BUILD_VECTOR)
44000 if (N00Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
44001 N01Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
44002 N10Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
44003 N11Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
44098 if (Op0.getOpcode() == ISD::ZERO_EXTEND &&
44106 if (Op1.getOpcode() == ISD::ZERO_EXTEND &&
44139 if (Op0.getOpcode() == ISD::UMAX) {
44149 } else if (Op1.getOpcode() == ISD::UMIN) {
44217 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
44302 if (Op0.getOpcode() == X86ISD::VBROADCAST ||
44303 Op0.getOpcode() == X86ISD::SUBV_BROADCAST)
44304 return DAG.getNode(Op0.getOpcode(), DL, VT, Op0.getOperand(0));
44307 if (Op0.getOpcode() == X86ISD::MOVDDUP && VT == MVT::v4f64 &&
44315 if (Op0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
44328 return Op.getOpcode() == Op0.getOpcode();
44328 return Op.getOpcode() == Op0.getOpcode();
44331 switch (Op0.getOpcode()) {
44340 return DAG.getNode(Op0.getOpcode(), DL, VT,
44368 return DAG.getNode(Op0.getOpcode(), DL, VT,
44428 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR &&
44441 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && IdxVal == 0 &&
44443 SubVec.getOperand(0).getOpcode() == ISD::INSERT_SUBVECTOR) {
44460 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
44499 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST)
44505 SubVec.getOpcode() == X86ISD::VBROADCAST_LOAD) {
44529 if (Sel.getOpcode() != ISD::VSELECT ||
44603 InVecVT.getSizeInBits() == 256 && InVecBC.getOpcode() == ISD::AND) {
44609 return peekThroughBitcasts(NotOp).getOpcode() == ISD::CONCAT_VECTORS;
44637 if (InVec.getOpcode() == ISD::BUILD_VECTOR)
44671 InVec.getOpcode() == ISD::INSERT_SUBVECTOR && IdxVal == 0 &&
44684 if (InVec.getOpcode() == X86ISD::VBROADCAST && InVec.hasOneUse() &&
44688 if (InVec.getOpcode() == X86ISD::VBROADCAST_LOAD && InVec.hasOneUse()) {
44705 unsigned InOpcode = InVec.getOpcode();
44758 if (VT == MVT::v1i1 && Src.getOpcode() == ISD::AND && Src.hasOneUse())
44765 if (VT == MVT::v1i1 && Src.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
44775 if (VT == MVT::v2i64 && Src.getOpcode() == ISD::ANY_EXTEND &&
44815 (LHS.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG ||
44816 LHS.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) &&
44825 (RHS.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG ||
44826 RHS.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) &&
45103 bool Is8BitMulByConstant = VT == MVT::i8 && Op.getOpcode() == ISD::MUL &&
45125 if (!Load.hasOneUse() || Load.getOpcode() != ISD::ATOMIC_LOAD)
45138 switch (Op.getOpcode()) {
45166 (Op.getOpcode() != ISD::MUL && IsFoldableRMW(N1, Op))))
45170 (Op.getOpcode() != ISD::MUL && IsFoldableRMW(N0, Op))))
lib/Target/XCore/XCoreISelDAGToDAG.cpp 94 if (Addr.getOpcode() == ISD::ADD) {
116 switch (Op.getOpcode()) {
lib/Target/XCore/XCoreISelLowering.cpp 179 if (Val.getOpcode() != ISD::LOAD)
198 switch (Op.getOpcode())
541 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
558 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
581 if (Op.getOpcode() != ISD::ADD)
587 if (N0.getOpcode() == ISD::ADD) {
590 } else if (N1.getOpcode() == ISD::ADD) {
598 if (OtherOp.getOpcode() == ISD::MUL) {
608 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
618 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
636 if (N->getOperand(0).getOpcode() == ISD::MUL) {
639 } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
1821 switch (Op.getOpcode()) {