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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/LiveRegUnits.h 97 if (UnitMask.none() || (UnitMask & Mask).any())
lib/CodeGen/DetectDeadLanes.cpp 210 if ((UsedLanes & ~PrevUsedLanes).none())
257 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
303 if ((DefinedLanes & ~PrevDefinedLanes).none())
462 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none();
462 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none();
lib/CodeGen/LiveInterval.cpp 908 if ((TRI.getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
931 LaneBitmask Matching = SRMask & LaneMask;
942 SR.LaneMask = SRMask & ~Matching;
973 assert((VRegMask & LaneMask).any());
981 LaneBitmask UndefMask = VRegMask & ~DefMask;
982 if ((UndefMask & LaneMask).any()) {
1085 assert((Mask & SR.LaneMask).none());
1089 assert((Mask & ~MaxMask).none());
lib/CodeGen/LiveIntervals.cpp 373 if ((SR.LaneMask & M).any()) {
559 if ((LaneMask & SR.LaneMask).none())
784 if ((UseMask & ~DefinedLanesMask).any())
999 if ((S.LaneMask & LaneMask).none())
1409 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none())
1519 if ((Mask & LaneMask).none())
lib/CodeGen/LivePhysRegs.cpp 169 if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any())
lib/CodeGen/LiveRangeCalc.cpp 183 if ((SLM & Mask).none())
lib/CodeGen/LiveRangeEdit.cpp 253 if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
lib/CodeGen/LiveRegMatrix.cpp 87 if ((S.LaneMask & Mask).any()) {
lib/CodeGen/MachineBasicBlock.cpp 469 return I != livein_end() && (I->LaneMask & LaneMask).any();
lib/CodeGen/MachineVerifier.cpp 1981 if ((MOMask & SR.LaneMask).none())
1989 if ((LiveInMask & MOMask).none()) {
2083 if ((SR.LaneMask & MOMask).none())
2427 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
2572 if (LaneMask.any() && (LaneMask & SLM).none())
2688 if ((Mask & SR.LaneMask).any()) {
2692 if ((SR.LaneMask & ~MaxMask).any()) {
lib/CodeGen/PeepholeOptimizer.cpp 1967 !(TRI->getSubRegIndexLaneMask(DefSubReg) &
lib/CodeGen/RegisterCoalescer.cpp 958 if ((SB.LaneMask & MaskA).any())
1414 if ((SR.LaneMask & DstMask).none()) {
1536 if ((SR.LaneMask & SrcMask).none())
1575 if ((SR.LaneMask & DstMask).none())
1597 if ((SR.LaneMask & UseMask).none())
1632 if ((S.LaneMask & Mask).none())
1936 if ((S.LaneMask & ShrinkMask).none())
2431 if ((SMask & LaneMask).none())
2580 if ((V.ValidLanes & OtherV.ValidLanes).any())
2631 && (V.WriteLanes & (OtherV.ValidLanes | OtherV.WriteLanes)).none())
2679 if ((V.WriteLanes & OtherV.ValidLanes).none())
2700 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes).none())
2750 (OtherV.WriteLanes & ~V.ValidLanes).any()) {
2833 if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())
2858 LaneBitmask TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
3736 assert((S.LaneMask & ~MaxMask).none());
lib/CodeGen/RegisterPressure.cpp 53 assert((PrevMask & ~NewMask).none() && "Must not remove bits");
610 AddFlagsMI != nullptr && (LiveAfter & ~I->LaneMask).none())
613 LaneBitmask ActualDef = I->LaneMask & LiveAfter;
624 LaneBitmask LaneMask = I->LaneMask & LiveBefore;
776 LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
778 LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
845 (LiveRegs.contains(RegUnit) & Def.LaneMask).none())
916 LaneBitmask LiveIn = Use.LaneMask & ~LiveMask;
927 decreaseRegPressure(Reg, LiveMask, LiveMask & ~LastUseMask);
1067 LaneBitmask LiveAfter = (LiveLanes & ~DefLanes) | UseLanes;
1313 LaneBitmask NewMask = LiveMask & ~LastUseMask;
lib/CodeGen/RenameIndependentSubregs.cpp 186 if ((SR.LaneMask & LaneMask).none())
231 if ((SR.LaneMask & LaneMask).none())
lib/CodeGen/ScheduleDAGInstrs.cpp 379 return (RegUse->LaneMask & getLaneMaskForMO(MO)).none();
431 if ((LaneMask & KillLaneMask).none()) {
436 if ((LaneMask & DefLaneMask).any()) {
471 if ((V2SU.LaneMask & LaneMask).none())
490 LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask;
491 LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
523 if ((PrevDefLaneMask & LaneMask).none())
lib/CodeGen/SplitKit.cpp 451 if ((S.LaneMask & LM).any())
574 if ((SubRegMask & ~LaneMask).any())
594 LaneBitmask LanesLeft = LaneMask & ~(TRI.getSubRegIndexLaneMask(BestIdx));
608 int Cover = (SubRegMask & LanesLeft).getNumLanes()
609 - (SubRegMask & ~LanesLeft).getNumLanes();
1380 if ((S.LaneMask & LM).none())
lib/CodeGen/VirtRegMap.cpp 368 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
lib/Target/AMDGPU/GCNRegPressure.cpp 127 Sign * (~PrevMask & NewMask).getNumLanes();
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 175 if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
175 if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
193 if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
193 if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
234 if ((Conflict->second.second & Mask).any())
lib/Target/AMDGPU/SIRegisterInfo.cpp 1881 if ((S.LaneMask & SubLanes) == SubLanes) {
lib/Target/AMDGPU/SIShrinkInstructions.cpp 401 LaneBitmask Overlap = TRI.getSubRegIndexLaneMask(SubReg) &
lib/Target/Hexagon/HexagonBlockRanges.cpp 246 if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any())
lib/Target/Hexagon/HexagonExpandCondsets.cpp 324 if ((SLM & LM) == SLM) {
379 LaneBitmask A = SLM & LM;
lib/Target/Hexagon/RDFCopy.cpp 124 if ((RC.LaneMask & RR.Mask) == RC.LaneMask)
lib/Target/Hexagon/RDFGraph.cpp 982 LaneBitmask M = AR.Mask & BR.Mask;
lib/Target/Hexagon/RDFLiveness.cpp 649 LaneBitmask M = R.Mask & V.second;
867 if ((M & I.LaneMask).any())
lib/Target/Hexagon/RDFRegisters.cpp 141 if (PA.second.any() && (PA.second & RA.Mask).none()) {
147 if (PB.second.any() && (PB.second & RB.Mask).none()) {
172 if (RC != nullptr && (RR.Mask & RC->LaneMask) == RC->LaneMask)
183 if ((SM & RR.Mask).none())
235 return RegisterRef(R, M & RCM);
246 if (P.second.none() || (P.second & RR.Mask).any())
261 if (P.second.none() || (P.second & RR.Mask).any())
276 if (P.second.none() || (P.second & RR.Mask).any())