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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/MC/MCInstrDesc.h 206 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
208 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
230 const_opInfo_iterator opInfo_begin() const { return OpInfo; }
231 const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
613 if (OpInfo[i].isPredicate())
lib/CodeGen/GlobalISel/LegalizerInfo.cpp 480 const MCOperandInfo *OpInfo = MI.getDesc().OpInfo;
lib/CodeGen/MachineInstr.cpp 1028 if (MCID.OpInfo[i].isPredicate())
1432 auto &OpInfo = getDesc().OpInfo[OpIdx];
lib/CodeGen/MachineVerifier.cpp 928 if (!MCID.OpInfo[I].isGenericType())
932 size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
1602 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1610 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 219 if (II.OpInfo[i].isOptionalDef()) {
305 MCID.OpInfo[IIOpNum].isOptionalDef();
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 1419 if (MCID.OpInfo[i].isOptionalDef()) {
lib/CodeGen/TargetInstrInfo.cpp 51 short RegClass = MCID.OpInfo[OpNum].RegClass;
52 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
332 if (MCID.OpInfo[i].isPredicate()) {
lib/CodeGen/TargetSchedule.cpp 242 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
lib/MC/MCInstrAnalysis.cpp 29 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 518 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass;
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp 319 if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) {
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 570 int RegClass = Desc.OpInfo[OpIdx].RegClass;
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 1712 uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType;
2759 const unsigned OperandType = Desc.OpInfo[OpIdx].OperandType;
2859 if (Desc.OpInfo[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)
6185 return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS
6189 && Desc.OpInfo[OpNum + 1].RegClass != -1
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 551 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
574 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 680 VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
705 AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256);
711 if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64)
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 520 switch (Desc.OpInfo[OpNo].OperandType) {
578 int RCID = Desc.OpInfo[OpNo].RegClass;
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp 118 Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp 323 if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
382 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
492 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
lib/Target/AMDGPU/SIFoldOperands.cpp 161 return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
217 switch (TII.get(Opcode).OpInfo[OpNo].OperandType) {
487 const MCOperandInfo *OpInfo = Desc.OpInfo;
826 UseDesc.OpInfo[UseOpIdx].RegClass == -1)
842 TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);
lib/Target/AMDGPU/SIISelLowering.cpp10399 if (const MCOperandInfo *OpInfo = MI.getDesc().OpInfo) {
lib/Target/AMDGPU/SIInstrInfo.cpp 2927 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
3241 int RegClass = Desc.OpInfo[i].RegClass;
3243 switch (Desc.OpInfo[i].OperandType) {
3451 if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
3499 if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
3534 !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
3537 !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
3812 Desc.OpInfo[OpNo].RegClass == -1) {
3820 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
3831 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
3954 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
3978 usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
3983 } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
3987 isLiteralConstantLike(Op, InstDesc.OpInfo[i])) {
4028 isLiteralConstantLike(Src0, InstrDesc.OpInfo[Src0Idx])))
4061 if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
4092 !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
4171 if (!isLiteralConstantLike(MO, get(Opc).OpInfo[Idx]))
4671 unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;
5814 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
5997 if (isLiteralConstantLike(MI.getOperand(Src0Idx), Desc.OpInfo[Src0Idx]))
6004 if (isLiteralConstantLike(MI.getOperand(Src1Idx), Desc.OpInfo[Src1Idx]))
6011 if (isLiteralConstantLike(MI.getOperand(Src2Idx), Desc.OpInfo[Src2Idx]))
6265 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;
lib/Target/AMDGPU/SIInstrInfo.h 709 if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
713 return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
720 return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
725 if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
737 return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
804 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
1026 return RI.getRegClass(TID.OpInfo[OpNum].RegClass);
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 1182 if (Desc.OpInfo[I].RegClass == -1 ||
1183 !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 1041 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1048 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1072 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1135 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h 616 return getOperandSize(Desc.OpInfo[OpNo]);
lib/Target/ARM/ARMBaseInstrInfo.cpp 2262 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
lib/Target/ARM/ARMISelLowering.cpp10774 if (!MI.hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 7285 if (ARM::isVpred(MCID.OpInfo[i].OperandType))
7338 if (MCID.OpInfo[i].isPredicate()) {
10196 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
10268 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 730 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
746 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
824 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
888 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp 268 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
298 if (Info->get(Inst.getOpcode()).OpInfo[OpId].OperandType !=
lib/Target/ARM/Thumb2InstrInfo.cpp 708 if (!MCID.OpInfo)
712 if (ARM::isVpred(MCID.OpInfo[i].OperandType))
lib/Target/ARM/Thumb2SizeReduction.cpp 831 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
833 if (SkipPred && MCID.OpInfo[i].isPredicate())
867 if (MCID.OpInfo[i].isPredicate())
877 !MCID.OpInfo[i].isPredicate()) {
938 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
948 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp 103 const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).OpInfo[OpNo];
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp 456 if (Desc.OpInfo[std::get<1>(Producer)].RegClass ==
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp 822 if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
lib/Target/Lanai/LanaiInstrInfo.cpp 519 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp 101 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType ==
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 2073 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
2107 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
3609 int16_t DstRegClass = Desc.OpInfo[0].RegClass;
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp 145 switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
lib/Target/PowerPC/PPCInstrInfo.cpp 1355 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
lib/Target/PowerPC/PPCInstrInfo.h 469 int16_t regClass = Desc.OpInfo[OpNo].RegClass;
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp 158 if (Desc.OpInfo[I].OperandType != WebAssembly::OPERAND_BASIC_BLOCK)
228 const MCOperandInfo &Info = Desc.OpInfo[OpNo];
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp 91 const MCOperandInfo &Info = Desc.OpInfo[I];
129 const MCOperandInfo &Info = Desc.OpInfo[I];
142 const MCOperandInfo &Info = Desc.OpInfo[I];
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 234 const MCOperandInfo &Info = Desc.OpInfo[I];
lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp 65 assert(MI.getDesc().OpInfo[OperandNo].OperandType ==
lib/Target/X86/X86MCInstLower.cpp 2147 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2219 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2250 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2267 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);