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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/MachineInstr.h 1555 void addOperand(const MachineOperand &Op);
References
lib/CodeGen/ExpandPostRAPseudos.cpp 72 CopyMI->addOperand(MO);
lib/CodeGen/LiveVariables.cpp 247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
lib/CodeGen/MachineInstr.cpp 1841 addOperand(MachineOperand::CreateReg(IncomingReg,
1908 addOperand(MachineOperand::CreateReg(Reg,
1945 addOperand(MachineOperand::CreateReg(Reg,
lib/CodeGen/MachineOutliner.cpp 1254 CallInst->addOperand(MachineOperand::CreateReg(
lib/CodeGen/ModuloSchedule.cpp 1643 MI.addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/false));
1644 MI.addOperand(MachineOperand::CreateMBB(*PI));
lib/CodeGen/RegisterCoalescer.cpp 1434 NewMI.addOperand(MachineOperand::CreateReg(
1464 NewMI.addOperand(MO);
lib/Target/AArch64/AArch64InstructionSelector.cpp 1683 I.addOperand(MachineOperand::CreateImm(0));
1684 I.addOperand(MachineOperand::CreateImm(0));
1787 I.addOperand(MachineOperand::CreateImm(Offset));
lib/Target/AMDGPU/SIFixupVectorISel.cpp 193 NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::offset));
204 NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::slc));
lib/Target/AMDGPU/SIInstrInfo.cpp 3910 Inst.addOperand(Op1);
4312 Copy->addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
5026 Inst.addOperand(MachineOperand::CreateImm(0));
5027 Inst.addOperand(MachineOperand::CreateImm(Size));
5032 Inst.addOperand(MachineOperand::CreateImm(0));
5049 Inst.addOperand(MachineOperand::CreateImm(Offset));
5050 Inst.addOperand(MachineOperand::CreateImm(BitWidth));
5124 Inst.addOperand(MachineOperand::CreateImm(0)); // clamp bit
lib/Target/AMDGPU/SILowerControlFlow.cpp 489 MI.addOperand(Ops[UniqueOpndIdx]);
lib/Target/AMDGPU/SIWholeQuadMode.cpp 869 MI->addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
lib/Target/ARC/ARCOptAddrMode.cpp 459 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true));
461 Ldst.addOperand(Src);
462 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false));
463 Ldst.addOperand(NewOffset);
lib/Target/ARM/ARMExpandPseudoInsts.cpp 1206 NewMI->addOperand(MBBI->getOperand(i));
lib/Target/ARM/ARMISelLowering.cpp10745 MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
10750 MI.addOperand(MI.getOperand(1));
10764 MI.addOperand(MachineOperand::CreateImm(ARMCC::AL));
10765 MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/false));
lib/Target/ARM/Thumb2ITBlockPass.cpp 218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
lib/Target/ARM/Thumb2InstrInfo.cpp 514 MI.addOperand(MachineOperand::CreateReg(0, false));
545 MI.addOperand(MachineOperand::CreateReg(0, false));
lib/Target/Hexagon/HexagonBitSimplify.cpp 2004 MI->addOperand(MachineOperand::CreateImm(V));
lib/Target/Hexagon/HexagonConstPropagation.cpp 3160 BrI.addOperand(Op);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 852 PN->addOperand(MachineOperand::CreateReg(MuxR, false, false, false, false,
854 PN->addOperand(MachineOperand::CreateMBB(FP.SplitB));
lib/Target/Hexagon/HexagonFrameLowering.cpp 538 RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
820 RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
2413 MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1909 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true));
1922 NewPN->addOperand(MO);
1923 NewPN->addOperand(MachineOperand::CreateMBB(PredB));
1935 PN->addOperand(MachineOperand::CreateReg(NewPR, false));
1936 PN->addOperand(MachineOperand::CreateMBB(NewPH));
lib/Target/Hexagon/HexagonInstrInfo.cpp 1601 MI.addOperand(T->getOperand(i));
4438 MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
lib/Target/Hexagon/HexagonPeephole.cpp 219 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
226 MI.addOperand(MachineOperand::CreateReg(
lib/Target/Hexagon/HexagonSplitDouble.cpp 602 NewI->addOperand(Op);
624 NewI->addOperand(CO);
lib/Target/Mips/MipsBranchExpansion.cpp 714 I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
lib/Target/Mips/MipsConstantIslandPass.cpp 1665 I->addOperand(MachineOperand::CreateCPI(index, 0));
1666 I->addOperand(MachineOperand::CreateImm(4));
lib/Target/Mips/MipsISelLowering.cpp 3008 MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR));
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 171 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
178 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
lib/Target/PowerPC/PPCISelLowering.cpp10865 MI.addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
lib/Target/PowerPC/PPCInstrInfo.cpp 3420 MI.addOperand(MOp2);
3421 MI.addOperand(MOp1);
3432 MI.addOperand(MOp2);
3436 MI.addOperand(MOp1);
3438 MI.addOperand(MOps.back());
3681 MI.addOperand(*ImmMO);
3684 MI.addOperand(MO);
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 118 Addi->addOperand(MI.getOperand(2));
127 Call->addOperand(MI.getOperand(3));
lib/Target/PowerPC/PPCTOCRegDeps.cpp 121 MI.addOperand(MachineOperand::CreateReg(TOCReg,
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 246 Tail.addOperand(ImmOp);
lib/Target/SystemZ/SystemZISelLowering.cpp 7487 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
7496 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
7501 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp 139 MI.addOperand(MO);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 85 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK,
91 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK,
108 MI->addOperand(MachineOperand::CreateImm(0));
111 MI->addOperand(MachineOperand::CreateImm(0));
116 MI->addOperand(MachineOperand::CreateFPImm(Val));
121 MI->addOperand(MachineOperand::CreateFPImm(Val));
125 MI->addOperand(MachineOperand::CreateReg(TempReg, false));
lib/Target/X86/X86CallFrameOptimization.cpp 564 Push->addOperand(DefMov->getOperand(i));
lib/Target/X86/X86ExpandPseudo.cpp 365 NewInstr->addOperand(MBBI->getOperand(Idx));
lib/Target/X86/X86FloatingPoint.cpp 1104 MI.addOperand(
1150 MI.addOperand(
lib/Target/X86/X86InstrInfo.cpp 1666 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1677 WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2462 MIB->addOperand(TailCall.getOperand(0)); // Destination.
2464 MIB->addOperand(BranchCond[0]); // Condition.
lib/Target/X86/X86InstructionSelector.cpp 578 I.addOperand(InxOp); // set IndexReg
lib/Target/XCore/XCoreFrameLowering.cpp 404 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands