reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
422 Def = MRI.getVRegDef(Reg); 1808 assert(Def->isCopy() && "Invalid definition"); 1813 assert(Def->getNumOperands() - Def->getNumImplicitOperands() == 2 && 1813 assert(Def->getNumOperands() - Def->getNumImplicitOperands() == 2 && 1815 assert(!Def->hasImplicitDef() && "Only implicit uses are allowed"); 1817 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) 1822 const MachineOperand &Src = Def->getOperand(1); 1829 assert(Def->isBitcast() && "Invalid definition"); 1832 if (Def->mayRaiseFPException() || Def->hasUnmodeledSideEffects()) 1832 if (Def->mayRaiseFPException() || Def->hasUnmodeledSideEffects()) 1836 if (Def->getDesc().getNumDefs() != 1) 1838 const MachineOperand DefOp = Def->getOperand(DefIdx); 1844 unsigned SrcIdx = Def->getNumOperands(); 1847 const MachineOperand &MO = Def->getOperand(OpIdx); 1862 if (SrcIdx >= Def->getNumOperands()) 1872 const MachineOperand &Src = Def->getOperand(SrcIdx); 1879 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && 1879 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && 1882 if (Def->getOperand(DefIdx).getSubReg()) 1905 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) 1923 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && 1923 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && 1926 if (Def->getOperand(DefIdx).getSubReg()) 1939 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) 1955 const MachineOperand &MODef = Def->getOperand(DefIdx); 1976 assert((Def->isExtractSubreg() || 1977 Def->isExtractSubregLike()) && "Invalid definition"); 1992 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg)) 2005 assert(Def->isSubregToReg() && "Invalid definition"); 2013 if (DefSubReg != Def->getOperand(3).getImm()) 2017 if (Def->getOperand(2).getSubReg()) 2020 return ValueTrackerResult(Def->getOperand(2).getReg(), 2021 Def->getOperand(3).getImm()); 2026 assert(Def->isPHI() && "Invalid definition"); 2031 if (Def->getOperand(0).getSubReg() != DefSubReg) 2035 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) { 2036 const MachineOperand &MO = Def->getOperand(i); 2049 assert(Def && "This method needs a valid definition"); 2051 assert(((Def->getOperand(DefIdx).isDef() && 2052 (DefIdx < Def->getDesc().getNumDefs() || 2053 Def->getDesc().isVariadic())) || 2054 Def->getOperand(DefIdx).isImplicit()) && 2056 if (Def->isCopy()) 2058 if (Def->isBitcast()) 2064 if (Def->isRegSequence() || Def->isRegSequenceLike()) 2064 if (Def->isRegSequence() || Def->isRegSequenceLike()) 2066 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) 2066 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) 2068 if (Def->isExtractSubreg() || Def->isExtractSubregLike()) 2068 if (Def->isExtractSubreg() || Def->isExtractSubregLike()) 2070 if (Def->isSubregToReg()) 2072 if (Def->isPHI()) 2080 if (!Def) 2093 Res.setInst(Def); 2100 Def = DI->getParent(); 2104 Def = nullptr; 2112 Def = nullptr;