|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1965 SDValue Zero = DAG.getConstant(0, DL, VT);
1966 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1969 if (SDValue Res = LowerDIVREM24(Op, DAG, true))
1974 DAG.ComputeNumSignBits(LHS) > 32 &&
1975 DAG.ComputeNumSignBits(RHS) > 32) {
1976 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1979 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1980 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1981 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1981 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1984 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1985 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1987 return DAG.getMergeValues(Res, DL);
1990 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1991 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1992 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1995 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1996 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1998 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1999 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
2001 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
2001 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
2004 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
2005 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
2007 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
2008 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
2014 return DAG.getMergeValues(Res, DL);