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References

lib/Target/AMDGPU/AMDGPUISelLowering.cpp
 3872   SelectionDAG &DAG = DCI.DAG;
 3940     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
 3943     return performShlCombine(N, DCI);
 3946     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
 3949     return performSrlCombine(N, DCI);
 3952     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
 3955     return performSraCombine(N, DCI);
 3958     return performTruncateCombine(N, DCI);
 3960     return performMulCombine(N, DCI);
 3962     return performMulhsCombine(N, DCI);
 3964     return performMulhuCombine(N, DCI);
 3969     if (SDValue V = simplifyI24(N, DCI))
 3975     return performMulLoHi24Combine(N, DCI);
 3977     return performSelectCombine(N, DCI);
 3979     return performFNegCombine(N, DCI);
 3981     return performFAbsCombine(N, DCI);
 4055       TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
 4056                                             !DCI.isBeforeLegalizeOps());
 4060         DCI.CommitTargetLoweringOpt(TLO);
 4067     return performLoadCombine(N, DCI);
 4069     return performStoreCombine(N, DCI);
 4072     return performRcpCombine(N, DCI);
 4075     return performAssertSZExtCombine(N, DCI);
 4077     return performIntrinsicWOChainCombine(N, DCI);