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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 2416 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
2417 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
2419 SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
2420 L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
2427 SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
2428 SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
2429 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
2430 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
2432 SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
2433 SDValue E = DAG.getSelect(SL, MVT::i32,
2434 DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
2435 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
2438 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
2439 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2440 DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
2442 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
2443 DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
2445 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
2446 U, DAG.getConstant(40, SL, MVT::i64));
2448 SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
2449 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2449 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2450 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl));
2452 SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
2453 SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
2454 SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
2456 SDValue One = DAG.getConstant(1, SL, MVT::i32);
2458 SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
2460 SDValue R = DAG.getSelect(SL, MVT::i32,
2463 DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
2464 R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
2465 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
2470 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
2471 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
2471 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);