reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
528 const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg); 536 BuildMI(MBB, MI, DL, get(Opc), DestReg) 544 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg) 550 if (DestReg == AMDGPU::VCC_LO) { 566 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc); 570 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) 576 if (DestReg == AMDGPU::VCC) { 592 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc); 596 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) 601 if (DestReg == AMDGPU::SCC) { 639 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg) 655 unsigned RegNo = DestReg % 3; 671 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg) 676 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg) 694 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc); 705 bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg); 715 copyPhysReg(MBB, MI, DL, RI.getSubReg(DestReg, SubIdx), 721 get(Opcode), RI.getSubReg(DestReg, SubIdx)); 726 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);