reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/SIInstrInfo.cpp
  531     assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
  532            AMDGPU::SReg_32RegClass.contains(SrcReg) ||
  533            AMDGPU::AGPR_32RegClass.contains(SrcReg));
  534     unsigned Opc = AMDGPU::AGPR_32RegClass.contains(SrcReg) ?
  537       .addReg(SrcReg, getKillRegState(KillSrc));
  543     if (SrcReg == AMDGPU::SCC) {
  551       if (AMDGPU::SReg_32RegClass.contains(SrcReg)) {
  553           .addReg(SrcReg, getKillRegState(KillSrc));
  556         assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
  559           .addReg(SrcReg, getKillRegState(KillSrc));
  565     if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
  566       reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
  571             .addReg(SrcReg, getKillRegState(KillSrc));
  577       if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
  579           .addReg(SrcReg, getKillRegState(KillSrc));
  582         assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
  585           .addReg(SrcReg, getKillRegState(KillSrc));
  591     if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
  592       reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
  597             .addReg(SrcReg, getKillRegState(KillSrc));
  602     assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
  604       .addReg(SrcReg, getKillRegState(KillSrc))
  610     assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
  611            AMDGPU::SReg_32RegClass.contains(SrcReg) ||
  612            AMDGPU::AGPR_32RegClass.contains(SrcReg));
  613     if (!AMDGPU::VGPR_32RegClass.contains(SrcReg)) {
  617         if (!Def->definesRegister(SrcReg, &RI))
  670       copyPhysReg(MBB, MI, DL, Tmp, SrcReg, KillSrc);
  677       .addReg(SrcReg, getKillRegState(KillSrc));
  693     if (!RI.isSGPRClass(RI.getPhysRegClass(SrcReg))) {
  694       reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
  698     Opcode = RI.hasVGPRs(RI.getPhysRegClass(SrcReg)) ?
  700   } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(RI.getPhysRegClass(SrcReg))) {
  705   bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg);
  716                   RI.getSubReg(SrcReg, SubIdx), KillSrc);
  723     Builder.addReg(RI.getSubReg(SrcReg, SubIdx));
  729     Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);