reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1243 const MachineFunction &MF = *MI->getParent()->getParent(); 1248 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) { 1255 MI->getFlag(MachineInstr::FrameSetup)) 1256 EmitUnwindingInstruction(MI); 1259 if (emitPseudoExpansionLowering(*OutStreamer, MI)) 1262 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) && 1266 unsigned Opc = MI->getOpcode(); 1274 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex()); 1275 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() == 1277 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR 1279 .addReg(MI->getOperand(0).getReg()) 1282 .addImm(MI->getOperand(2).getImm()) 1283 .addReg(MI->getOperand(3).getReg())); 1290 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex()); 1291 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() == 1293 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR 1295 .addReg(MI->getOperand(0).getReg()) 1298 .addImm(MI->getOperand(2).getImm()) 1299 .addReg(MI->getOperand(3).getReg())); 1316 .addReg(MI->getOperand(0).getReg())); 1329 Register TReg = MI->getOperand(0).getReg(); 1362 .addReg(MI->getOperand(0).getReg()) 1380 const MachineOperand &Op = MI->getOperand(0); 1396 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 1398 unsigned TF = MI->getOperand(1).getTargetFlags(); 1399 const GlobalValue *GV = MI->getOperand(1).getGlobal(); 1405 MI->getOperand(2).getImm(), OutContext); 1428 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 1429 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg())); 1431 unsigned TF = MI->getOperand(2).getTargetFlags(); 1432 const GlobalValue *GV = MI->getOperand(2).getGlobal(); 1438 MI->getOperand(3).getImm(), OutContext); 1464 MI->getOperand(0).getIndex(), OutContext), 1468 if (MI->getOperand(1).isReg()) { 1470 MCInst.addReg(MI->getOperand(1).getReg()); 1474 if (MI->getOperand(1).isMBB()) 1476 MI->getOperand(1).getMBB()->getSymbol(), OutContext); 1477 else if (MI->getOperand(1).isGlobal()) { 1478 const GlobalValue *GV = MI->getOperand(1).getGlobal(); 1480 GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext); 1481 } else if (MI->getOperand(1).isSymbol()) { 1483 GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()), 1494 MI->getOperand(2).getIndex(), OutContext), 1497 MCInst.addImm(MI->getOperand(3).getImm()); 1499 MCInst.addImm(MI->getOperand(2).getImm()) 1500 .addReg(MI->getOperand(3).getReg()); 1512 MI->getOperand(0).getIndex(), OutContext)); 1524 MI->getOperand(2).getImm(), OutContext)); 1528 .addReg(MI->getOperand(0).getReg()) 1529 .addReg(MI->getOperand(0).getReg()) 1545 MI->getOperand(2).getImm(), OutContext)); 1549 .addReg(MI->getOperand(0).getReg()) 1551 .addReg(MI->getOperand(1).getReg()) 1553 .addImm(MI->getOperand(3).getImm()) 1554 .addReg(MI->getOperand(4).getReg()) 1576 MI->getOperand(2).getImm(), OutContext)); 1580 switch (MI->getOpcode()) { 1593 .addReg(MI->getOperand(0).getReg()) 1595 .addReg(MI->getOperand(1).getReg()) 1598 .addImm(MI->getOperand(3).getImm()) 1599 .addReg(MI->getOperand(4).getReg())); 1612 unsigned LabelId = (unsigned)MI->getOperand(0).getImm(); 1613 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex(); 1631 EmitJumpTableAddrs(MI); 1634 EmitJumpTableInsts(MI); 1638 EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2); 1638 EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2); 1643 .addReg(MI->getOperand(0).getReg()) 1651 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH; 1653 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm())); 1655 .addReg(MI->getOperand(0).getReg()) 1656 .addReg(MI->getOperand(1).getReg()) 1665 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT; 1666 Register Base = MI->getOperand(0).getReg(); 1667 Register Idx = MI->getOperand(1).getReg(); 1668 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!"); 1737 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm())); 1751 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ? 1755 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 1770 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 1771 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm())); 1783 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 1784 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg())); 1785 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm())); 1796 .addReg(MI->getOperand(0).getReg()) 1797 .addReg(MI->getOperand(1).getReg()) 1806 OutStreamer->EmitZeros(MI->getOperand(1).getImm()); 1847 Register SrcReg = MI->getOperand(0).getReg(); 1848 Register ValReg = MI->getOperand(1).getReg(); 1913 Register SrcReg = MI->getOperand(0).getReg(); 1914 Register ValReg = MI->getOperand(1).getReg(); 1970 Register SrcReg = MI->getOperand(0).getReg(); 1971 Register ScratchReg = MI->getOperand(1).getReg(); 2030 Register SrcReg = MI->getOperand(0).getReg(); 2031 Register ScratchReg = MI->getOperand(1).getReg(); 2098 Register SrcReg = MI->getOperand(0).getReg(); 2124 LowerPATCHABLE_FUNCTION_ENTER(*MI); 2127 LowerPATCHABLE_FUNCTION_EXIT(*MI); 2130 LowerPATCHABLE_TAIL_CALL(*MI); 2135 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);