|
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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/ARM/ARMISelDAGToDAG.cpp 2918 SDLoc dl(N);
2920 if (N->isMachineOpcode()) {
2921 N->setNodeId(-1);
2925 switch (N->getOpcode()) {
2938 StoreSDNode *ST = cast<StoreSDNode>(N);
2959 ReplaceNode(N, ResNode);
2966 if (tryWriteRegister(N))
2970 if (tryReadRegister(N))
2975 if (tryInlineAsm(N))
2980 if (tryABSOp(N))
2985 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
3023 ReplaceNode(N, ResNode);
3032 int FI = cast<FrameIndexSDNode>(N)->getIndex();
3041 CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI,
3050 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3055 if (tryV6T2BitfieldExtractOp(N, false))
3060 if (tryV6T2BitfieldExtractOp(N, true))
3066 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
3073 SDValue V = N->getOperand(0);
3079 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
3084 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
3092 SDValue V = N->getOperand(0);
3098 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
3103 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
3111 if (tryV6T2BitfieldExtractOp(N, false))
3117 auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1));
3137 CurDAG->RepositionNode(N->getIterator(), NewImm.getNode());
3141 N->getOperand(0), NewImm, getAL(CurDAG, dl),
3143 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops));
3146 SDValue Ops[] = {N->getOperand(0), NewImm, getAL(CurDAG, dl),
3149 ReplaceNode(N,
3161 EVT VT = N->getValueType(0);
3169 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3169 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3187 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
3196 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
3196 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
3197 N->getOperand(2), N->getOperand(3),
3197 N->getOperand(2), N->getOperand(3),
3200 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, MVT::i32, Ops));
3205 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3205 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3205 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3206 N->getOperand(3), getAL(CurDAG, dl),
3209 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops));
3212 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3212 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3212 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3213 N->getOperand(3), getAL(CurDAG, dl),
3216 ReplaceNode(N, CurDAG->getMachineNode(
3224 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3224 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3224 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3225 N->getOperand(3), getAL(CurDAG, dl),
3228 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops));
3231 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3231 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3231 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3232 N->getOperand(3), getAL(CurDAG, dl),
3235 ReplaceNode(N, CurDAG->getMachineNode(
3246 if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI ||
3247 N->getOperand(2).getOpcode() != ARMISD::SUBC ||
3248 !SDValue(N, 1).use_empty())
3255 SDValue SmulLoHi = N->getOperand(1);
3256 SDValue Subc = N->getOperand(2);
3261 N->getOperand(1) != SmulLoHi.getValue(1) ||
3262 N->getOperand(2) != Subc.getValue(1))
3267 N->getOperand(0), getAL(CurDAG, dl),
3269 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops));
3273 if (Subtarget->hasMVEIntegerOps() && tryMVEIndexedLoad(N))
3276 if (tryT2IndexedLoad(N))
3279 if (tryT1IndexedLoad(N))
3281 } else if (tryARMIndexedLoad(N))
3288 SDValue Ops[] = { N->getOperand(1),
3289 N->getOperand(2),
3290 N->getOperand(0) };
3291 unsigned Opc = N->getOpcode() == ARMISD::WLS ?
3294 ReplaceUses(N, New);
3295 CurDAG->RemoveDeadNode(N);
3299 SDValue Ops[] = { N->getOperand(1),
3300 N->getOperand(2),
3301 N->getOperand(0) };
3305 ReplaceUses(N, Dec);
3306 CurDAG->RemoveDeadNode(N);
3324 SDValue Chain = N->getOperand(0);
3325 SDValue N1 = N->getOperand(1);
3326 SDValue N2 = N->getOperand(2);
3327 SDValue N3 = N->getOperand(3);
3328 SDValue InFlag = N->getOperand(4);
3358 ReplaceUses(N, LoopEnd);
3359 CurDAG->RemoveDeadNode(N);
3368 InFlag = N->getOperand(4);
3388 if (N->getNumValues() == 2) {
3390 ReplaceUses(SDValue(N, 1), InFlag);
3392 ReplaceUses(SDValue(N, 0),
3394 CurDAG->RemoveDeadNode(N);
3403 SDValue X = N->getOperand(0);
3404 auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1).getNode());
3429 CurDAG->MorphNodeTo(N, ARMISD::CMPZ, CurDAG->getVTList(MVT::Glue), Ops2);
3437 SDValue InFlag = N->getOperand(4);
3444 SDValue ARMcc = N->getOperand(2);
3458 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc,
3458 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc,
3459 N->getOperand(3), N->getOperand(4)};
3459 N->getOperand(3), N->getOperand(4)};
3460 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops);
3460 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops);
3470 EVT VT = N->getValueType(0);
3487 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3487 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3488 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
3493 EVT VT = N->getValueType(0);
3510 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3510 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3511 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
3516 EVT VT = N->getValueType(0);
3532 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3532 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3533 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
3537 EVT VecVT = N->getValueType(0);
3543 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
3543 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
3543 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
3549 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
3549 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
3549 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
3553 ReplaceNode(N,
3554 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
3554 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
3555 N->getOperand(2), N->getOperand(3)));
3555 N->getOperand(2), N->getOperand(3)));
3564 SelectVLDDup(N, /* IsIntrinsic= */ false, false, 1, DOpcodes, QOpcodes);
3571 SelectVLDDup(N, /* IsIntrinsic= */ false, false, 2, Opcodes);
3579 SelectVLDDup(N, /* IsIntrinsic= */ false, false, 3, Opcodes);
3587 SelectVLDDup(N, /* IsIntrinsic= */ false, false, 4, Opcodes);
3598 SelectVLDDup(N, /* IsIntrinsic= */ false, true, 1, DOpcodes, QOpcodes);
3606 SelectVLDDup(N, /* IsIntrinsic= */ false, true, 2, Opcodes);
3614 SelectVLDDup(N, /* IsIntrinsic= */ false, true, 3, Opcodes);
3622 SelectVLDDup(N, /* IsIntrinsic= */ false, true, 4, Opcodes);
3635 SelectVLD(N, true, 1, DOpcodes, QOpcodes, nullptr);
3647 SelectVLD(N, true, 2, DOpcodes, QOpcodes, nullptr);
3662 SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
3677 SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
3687 SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
3697 SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
3707 SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
3720 SelectVST(N, true, 1, DOpcodes, QOpcodes, nullptr);
3732 SelectVST(N, true, 2, DOpcodes, QOpcodes, nullptr);
3747 SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
3762 SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
3772 SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
3782 SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
3792 SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
3798 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
3805 SDLoc dl(N);
3806 SDValue Chain = N->getOperand(0);
3815 Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(), dl)); /* coproc */
3816 Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(3))->getZExtValue(), dl)); /* opc */
3817 Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(4))->getZExtValue(), dl)); /* CRm */
3832 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops));
3837 SDLoc dl(N);
3838 SDValue Chain = N->getOperand(0);
3839 SDValue MemAddr = N->getOperand(2);
3860 MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3865 if (!SDValue(N, 0).use_empty()) {
3876 ReplaceUses(SDValue(N, 0), Result);
3878 if (!SDValue(N, 1).use_empty()) {
3889 ReplaceUses(SDValue(N, 1), Result);
3891 ReplaceUses(SDValue(N, 2), OutChain);
3892 CurDAG->RemoveDeadNode(N);
3897 SDLoc dl(N);
3898 SDValue Chain = N->getOperand(0);
3899 SDValue Val0 = N->getOperand(2);
3900 SDValue Val1 = N->getOperand(3);
3901 SDValue MemAddr = N->getOperand(4);
3927 MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3930 ReplaceNode(N, St);
3939 SelectVLD(N, false, 1, DOpcodes, QOpcodes, nullptr);
3950 SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
3967 SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3984 SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3993 SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
4008 SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
4023 SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
4036 SelectVLDDup(N, /* IsIntrinsic= */ true, false, 2,
4052 SelectVLDDup(N, /* IsIntrinsic= */ true, false, 3,
4068 SelectVLDDup(N, /* IsIntrinsic= */ true, false, 4,
4079 SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
4089 SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
4099 SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
4108 SelectVST(N, false, 1, DOpcodes, QOpcodes, nullptr);
4119 SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
4136 SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
4153 SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
4162 SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
4177 SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
4192 SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
4202 SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
4212 SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
4222 SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
4230 SelectMVE_WB(N, Opcodes,
4242 SelectMVE_VLD(N, 2, Opcodes);
4256 SelectMVE_VLD(N, 4, Opcodes);
4264 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4270 SelectMVE_LongShift(N, ARM::MVE_URSHRL, true);
4275 SelectMVE_VADCSBC(N, ARM::MVE_VADC, ARM::MVE_VADCI, true,
4283 SelectCMP_SWAP(N);
4287 SelectCode(N);