reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
7328 /* 15023*/ /*SwitchOpcode*/ 66|128,1/*194*/, TARGET_VAL(ARMISD::VSHRuIMM),// ->15221 7685 /* 15899*/ /*SwitchOpcode*/ 67|128,1/*195*/, TARGET_VAL(ARMISD::VSHRuIMM),// ->16098 46597 /*103375*/ OPC_SwitchOpcode /*2 cases */, 13|128,2/*269*/, TARGET_VAL(ARMISD::VSHRuIMM),// ->103649 47714 /*105917*/ /*SwitchOpcode*/ 95|128,3/*479*/, TARGET_VAL(ARMISD::VSHRuIMM),// ->106400gen/lib/Target/ARM/ARMGenFastISel.inc
6189 case ARMISD::VSHRuIMM: return fastEmit_ARMISD_VSHRuIMM_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6472 case ARMISD::VSHRuIMM: return fastEmit_ARMISD_VSHRuIMM_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1); 6881 case ARMISD::VSHRuIMM: return fastEmit_ARMISD_VSHRuIMM_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1); 7417 case ARMISD::VSHRuIMM: return fastEmit_ARMISD_VSHRuIMM_ri_Predicate_imm0_15(VT, RetVT, Op0, Op0IsKill, imm1);lib/Target/ARM/ARMISelLowering.cpp
1586 case ARMISD::VSHRuIMM: return "ARMISD::VSHRuIMM"; 5474 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64, 6059 (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM); 13621 : ARMISD::VSHRuIMM); 13817 (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);