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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/Hexagon/HexagonBitTracker.cpp 325 return rr0(eIMM(im(1), W0), Outputs);
381 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
383 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
383 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
387 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
387 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
391 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
395 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
396 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
401 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
405 RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
410 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
420 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
424 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
436 RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
442 return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
448 return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
450 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
450 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
454 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
454 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
458 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
484 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
489 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
499 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
503 RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
507 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
525 return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
533 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
533 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
537 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
537 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
549 return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
557 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
557 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
561 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
561 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
570 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
574 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
598 return rr0(eASL(rc(1), im(2)), Outputs);
603 return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
606 return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
609 return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
612 return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
615 return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
623 return rr0(eASR(rc(1), im(2)), Outputs);
628 return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
631 return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
634 return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
637 return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
643 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
647 int64_t S = im(2);
663 return rr0(eLSR(rc(1), im(2)), Outputs);
666 return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
669 return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
672 return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
675 return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
678 return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
682 RC[im(2)] = BT::BitValue::Zero;
687 RC[im(2)] = BT::BitValue::One;
692 uint16_t BX = im(2);
701 uint16_t BX = im(2);
714 uint16_t Wd = im(2), Of = im(3);
714 uint16_t Wd = im(2), Of = im(3);
730 uint16_t Wd = im(3), Of = im(4);
730 uint16_t Wd = im(3), Of = im(4);
950 BT::BitValue V = rc(1)[im(2)];