reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
170 if (OffsetReg == RR.Reg) { 292 if (LRExtReg == RR.Reg) {lib/Target/Hexagon/RDFCopy.cpp
48 assert(Register::isPhysicalRegister(DstR.Reg)); 49 assert(Register::isPhysicalRegister(SrcR.Reg)); 51 if (TRI.getMinimalPhysRegClass(DstR.Reg) != 52 TRI.getMinimalPhysRegClass(SrcR.Reg)) 123 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); 125 return RR.Reg; 126 for (MCSubRegIndexIterator S(RR.Reg, &TRI); S.isValid(); ++S)lib/Target/Hexagon/RDFGraph.cpp
59 if (P.Obj.Reg > 0 && P.Obj.Reg < TRI.getNumRegs()) 59 if (P.Obj.Reg > 0 && P.Obj.Reg < TRI.getNumRegs()) 60 OS << TRI.getName(P.Obj.Reg); 62 OS << '#' << P.Obj.Reg; 981 if (AR.Reg == BR.Reg) { 981 if (AR.Reg == BR.Reg) { 983 return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef(); 1058 DefM[RR.Reg].push(DA); 1059 Defined.insert(RR.Reg); 1060 for (RegisterId A : PRI.getAliasSet(RR.Reg)) { 1062 assert(A != RR.Reg); 1104 if (!Defined.insert(RR.Reg).second) { 1114 DefM[RR.Reg].push(DA); 1115 for (RegisterId A : PRI.getAliasSet(RR.Reg)) { 1117 assert(A != RR.Reg); 1628 auto F = DefM.find(RR.Reg); 1711 linkRefUp<UseNode*>(IA, PUA, DefM[RR.Reg]);lib/Target/Hexagon/RDFGraph.h
741 return { RR.Reg, LMI.getIndexForLaneMask(RR.Mask) }; 744 return { RR.Reg, LMI.getIndexForLaneMask(RR.Mask) };lib/Target/Hexagon/RDFLiveness.cpp
478 RealUses[R.Reg].insert({A.Id,R.Mask}); 652 if (RegisterRef SS = MidDefs.clearIn(RegisterRef(R.Reg, M))) { 653 NodeRefSet &RS = RealUseMap[P.first][SS.Reg]; 784 LOX[S.Reg].insert({D.Id, TM}); 847 B.addLiveIn({MCPhysReg(R.Reg), R.Mask}); 996 NodeRefSet &NewDefs = LiveIn[LRef.Reg]; // To be filled. 1079 LiveIn[RR.Reg].insert({D.Id,RR.Mask});lib/Target/Hexagon/RDFRegisters.cpp
132 assert(Register::isPhysicalRegister(RA.Reg)); 133 assert(Register::isPhysicalRegister(RB.Reg)); 135 MCRegUnitMaskIterator UMA(RA.Reg, &TRI); 136 MCRegUnitMaskIterator UMB(RB.Reg, &TRI); 163 assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); 163 assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); 164 const uint32_t *MB = getRegMaskBits(RM.Reg); 165 bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32)); 165 bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32)); 171 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; 181 for (MCSubRegIndexIterator SI(RR.Reg, &TRI); SI.isValid(); ++SI) { 198 assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg)); 198 assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg)); 200 const uint32_t *BM = getRegMaskBits(RM.Reg); 201 const uint32_t *BN = getRegMaskBits(RN.Reg); 226 if (RR.Reg == R) 228 if (unsigned Idx = TRI.getSubRegIndex(R, RR.Reg)) 230 if (unsigned Idx = TRI.getSubRegIndex(RR.Reg, R)) { 241 if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) 242 return Units.anyCommon(PRI.getMaskUnits(RR.Reg)); 244 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { 254 if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) { 255 BitVector T(PRI.getMaskUnits(RR.Reg)); 259 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { 269 if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) { 270 Units |= PRI.getMaskUnits(RR.Reg); 274 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { 376 Masks[R.Reg] |= R.Mask;lib/Target/Hexagon/RDFRegisters.h
80 return Reg != 0 && Mask.any(); 84 return Reg == RR.Reg && Mask == RR.Mask; 84 return Reg == RR.Reg && Mask == RR.Mask; 92 return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask); 92 return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask); 92 return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask); 92 return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask); 116 if (!isRegMaskId(RA.Reg)) 117 return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB); 118 return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB);