reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
2306 switch (Inst.getOpcode()) { 2310 return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2312 return expandLoadImm(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2315 assert(Inst.getOperand(0).isReg() && "expected register operand kind"); 2316 assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) && 2316 assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) && 2319 return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister, 2320 Inst.getOperand(1), 2321 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, 2327 assert(Inst.getOperand(0).isReg() && "expected register operand kind"); 2328 assert(Inst.getOperand(1).isReg() && "expected register operand kind"); 2329 assert((Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) && 2329 assert((Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) && 2332 return expandLoadAddress(Inst.getOperand(0).getReg(), 2333 Inst.getOperand(1).getReg(), Inst.getOperand(2), 2333 Inst.getOperand(1).getReg(), Inst.getOperand(2), 2334 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc, 2340 return expandUncondBranchMMPseudo(Inst, IDLoc, Out, STI) ? MER_Fail 2344 return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail 2348 return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2353 return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2386 return expandCondBranches(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2391 return expandDivRem(Inst, IDLoc, Out, STI, false, true) ? MER_Fail 2397 return expandDivRem(Inst, IDLoc, Out, STI, true, true) ? MER_Fail 2403 return expandDivRem(Inst, IDLoc, Out, STI, false, false) ? MER_Fail 2409 return expandDivRem(Inst, IDLoc, Out, STI, true, false) ? MER_Fail 2412 return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail 2415 return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail 2418 return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail 2422 return expandLoadSingleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail 2425 return expandLoadSingleImmToFPR(Inst, IDLoc, Out, STI) ? MER_Fail 2428 return expandLoadDoubleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail 2431 return expandLoadDoubleImmToFPR(Inst, true, IDLoc, Out, STI) ? MER_Fail 2434 return expandLoadDoubleImmToFPR(Inst, false, IDLoc, Out, STI) ? MER_Fail 2438 return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2440 return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2442 return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2445 return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2448 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2451 return expandSge(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2456 return expandSgeImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2461 return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2463 if (isInt<16>(Inst.getOperand(2).getImm())) { 2464 Inst.setOpcode(Mips::SLTi64); 2467 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2469 if (isInt<16>(Inst.getOperand(2).getImm())) { 2470 Inst.setOpcode(Mips::SLTiu64); 2473 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2478 if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && 2478 if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && 2479 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { 2479 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { 2480 int64_t ImmValue = Inst.getOperand(2).getImm(); 2483 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail 2490 if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && 2490 if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && 2491 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { 2491 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { 2492 int64_t ImmValue = Inst.getOperand(2).getImm(); 2495 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail 2501 return expandRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2504 return expandRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2507 return expandDRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2510 return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2512 return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2515 return expandMulImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2518 return expandMulO(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2521 return expandMulOU(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2523 return expandDMULMacro(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2526 return expandLoadStoreDMacro(Inst, IDLoc, Out, STI, 2527 Inst.getOpcode() == Mips::LDMacro) 2531 return expandStoreDM1Macro(Inst, IDLoc, Out, STI) 2535 return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2537 return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2547 return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;