reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. 111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) 119 if (Mips::CCRRegClass.contains(DestReg)) 121 else if (Mips::FGR32RegClass.contains(DestReg)) 123 else if (Mips::HI32RegClass.contains(DestReg)) 124 Opc = Mips::MTHI, DestReg = 0; 125 else if (Mips::LO32RegClass.contains(DestReg)) 126 Opc = Mips::MTLO, DestReg = 0; 127 else if (Mips::HI32DSPRegClass.contains(DestReg)) 129 else if (Mips::LO32DSPRegClass.contains(DestReg)) 131 else if (Mips::DSPCCRegClass.contains(DestReg)) { 134 .addReg(DestReg, RegState::ImplicitDefine); 136 } else if (Mips::MSACtrlRegClass.contains(DestReg)) { 138 .addReg(DestReg) 143 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 145 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) 147 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) 149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. 160 if (Mips::HI64RegClass.contains(DestReg)) 161 Opc = Mips::MTHI64, DestReg = 0; 162 else if (Mips::LO64RegClass.contains(DestReg)) 163 Opc = Mips::MTLO64, DestReg = 0; 164 else if (Mips::FGR64RegClass.contains(DestReg)) 167 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg 176 if (DestReg) 177 MIB.addReg(DestReg, RegState::Define);