reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
2133 auto &MBB = *MI.getParent(); 2134 auto DL = MI.getDebugLoc(); 2136 switch (MI.getOpcode()) { 2142 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); 2143 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 2143 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 2154 assert(MI.getOperand(2).isReg() && 2155 isAnImmediateOperand(MI.getOperand(1)) && 2157 return expandVSXMemPseudo(MI); 2166 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && 2166 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && 2168 return expandVSXMemPseudo(MI); 2174 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && 2174 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && 2176 return expandVSXMemPseudo(MI); 2179 Register TargetReg = MI.getOperand(0).getReg(); 2181 MI.setDesc(get(PPC::DFLOADf64)); 2182 return expandPostRAPseudo(MI); 2185 MI.setDesc(get(PPC::LD)); 2189 Register SrcReg = MI.getOperand(0).getReg(); 2192 MI.setDesc(get(PPC::DFSTOREf64)); 2193 return expandPostRAPseudo(MI); 2196 MI.setDesc(get(PPC::STD)); 2201 Register TargetReg = MI.getOperand(0).getReg(); 2203 MI.setDesc(get(PPC::LXSDX)); 2205 MI.setDesc(get(PPC::LDX)); 2209 Register SrcReg = MI.getOperand(0).getReg(); 2212 MI.setDesc(get(PPC::STXSDX)); 2215 MI.setDesc(get(PPC::STDX)); 2221 auto Val = MI.getOperand(0).getReg(); 2222 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val); 2223 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP)) 2227 MI.setDesc(get(PPC::ISYNC)); 2228 MI.RemoveOperand(0);