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| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @atomicrmw_xchg_i64(i64* %addr) { ret void }
define void @atomicrmw_add_i64(i64* %addr) { ret void }
define void @atomicrmw_add_i32(i64* %addr) { ret void }
define void @atomicrmw_sub_i32(i64* %addr) { ret void }
define void @atomicrmw_and_i32(i64* %addr) { ret void }
; nand isn't legal
define void @atomicrmw_or_i32(i64* %addr) { ret void }
define void @atomicrmw_xor_i32(i64* %addr) { ret void }
define void @atomicrmw_min_i32(i64* %addr) { ret void }
define void @atomicrmw_max_i32(i64* %addr) { ret void }
define void @atomicrmw_umin_i32(i64* %addr) { ret void }
define void @atomicrmw_umax_i32(i64* %addr) { ret void }
...
---
name: atomicrmw_xchg_i64
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_xchg_i64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
; CHECK: $x0 = COPY [[SWPX]]
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 1
%2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic 8 on %ir.addr)
$x0 = COPY %2(s64)
...
---
name: atomicrmw_add_i64
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_add_i64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
; CHECK: $x0 = COPY [[LDADDX]]
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 1
%2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
$x0 = COPY %2(s64)
...
---
name: atomicrmw_add_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_add_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
; CHECK: $w0 = COPY [[LDADDALW]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr)
$w0 = COPY %2(s32)
...
---
name: atomicrmw_sub_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_sub_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
; CHECK: $w0 = COPY [[LDADDALW]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr)
$w0 = COPY %2(s32)
...
---
name: atomicrmw_and_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_and_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[MOVi32imm]]
; CHECK: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire 4 on %ir.addr)
; CHECK: $w0 = COPY [[LDCLRAW]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire 4 on %ir.addr)
$w0 = COPY %2(s32)
...
---
name: atomicrmw_or_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_or_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[MOVi32imm]], [[COPY]] :: (load store release 4 on %ir.addr)
; CHECK: $w0 = COPY [[LDSETLW]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release 4 on %ir.addr)
$w0 = COPY %2(s32)
...
---
name: atomicrmw_xor_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_xor_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
; CHECK: $w0 = COPY [[LDEORALW]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel 4 on %ir.addr)
$w0 = COPY %2(s32)
...
---
name: atomicrmw_min_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_min_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
; CHECK: $w0 = COPY [[LDSMINALW]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel 4 on %ir.addr)
$w0 = COPY %2(s32)
...
---
name: atomicrmw_max_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_max_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
; CHECK: $w0 = COPY [[LDSMAXALW]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel 4 on %ir.addr)
$w0 = COPY %2(s32)
...
---
name: atomicrmw_umin_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_umin_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
; CHECK: $w0 = COPY [[LDUMINALW]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel 4 on %ir.addr)
$w0 = COPY %2(s32)
...
---
name: atomicrmw_umax_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: atomicrmw_umax_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
; CHECK: $w0 = COPY [[LDUMAXALW]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel 4 on %ir.addr)
$w0 = COPY %2(s32)
...
|