1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-unknown -O3 -verify-machineinstrs < %s | FileCheck %s
; Test cases are generated from:
; long long NAME(PARAM a, PARAM b) {
; if (LHS > RHS)
; return b;
; if (LHS < RHS)
; return a;\
; return a * b;
; }
; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
target datalayout = "e-m:e-i64:64-n32:64"
define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b__2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmn x8, #2 // =2
; CHECK-NEXT: b.le .LBB0_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret
entry:
%shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, -2
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, -2
%mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select
return: ; preds = %entry
ret i64 %b
}
define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b__1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: tbnz x8, #63, .LBB1_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: // %if.end
; CHECK-NEXT: cmn x8, #1 // =1
; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret
entry:
%shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, -1
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, -1
%mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select
return: ; preds = %entry
ret i64 %b
}
define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b_0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmp x8, #0 // =0
; CHECK-NEXT: b.le .LBB2_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret
entry:
%shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, 0
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, 0
%mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select
return: ; preds = %entry
ret i64 %b
}
define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmp x8, #1 // =1
; CHECK-NEXT: b.le .LBB3_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret
entry:
%shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, 1
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, 1
%mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select
return: ; preds = %entry
ret i64 %b
}
define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmp x8, #2 // =2
; CHECK-NEXT: b.le .LBB4_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB4_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret
entry:
%shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, 2
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, 2
%mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select
return: ; preds = %entry
ret i64 %b
}
define i64 @ll_a__2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a__2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn x0, #2 // =2
; CHECK-NEXT: b.le .LBB5_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB5_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i64 %a, -2
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, -2
%mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select
return: ; preds = %entry
ret i64 %b
}
define i64 @ll_a__1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a__1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: tbnz x0, #63, .LBB6_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB6_2: // %if.end
; CHECK-NEXT: cmn x0, #1 // =1
; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i64 %a, -1
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, -1
%mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select
return: ; preds = %entry
ret i64 %b
}
define i64 @ll_a_0(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp x0, #0 // =0
; CHECK-NEXT: b.le .LBB7_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB7_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i64 %a, 0
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, 0
%mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select
return: ; preds = %entry
ret i64 %b
}
define i64 @ll_a_1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp x0, #1 // =1
; CHECK-NEXT: b.le .LBB8_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB8_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i64 %a, 1
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, 1
%mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select
return: ; preds = %entry
ret i64 %b
}
define i64 @ll_a_2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp x0, #2 // =2
; CHECK-NEXT: b.le .LBB9_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB9_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i64 %a, 2
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, 2
%mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select
return: ; preds = %entry
ret i64 %b
}
define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_op_b__2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmn w8, #2 // =2
; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
%shl = shl i32 %a, %b
%cmp = icmp sgt i32 %shl, -2
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp eq i32 %shl, -2
%mul = select i1 %cmp2, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a
br label %return
return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0
}
define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_op_b__1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmn w8, #1 // =1
; CHECK-NEXT: csinc w9, w1, wzr, eq
; CHECK-NEXT: mul w9, w9, w0
; CHECK-NEXT: cmp w8, #0 // =0
; CHECK-NEXT: csel w8, w1, w9, ge
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
%shl = shl i32 %a, %b
%cmp = icmp sgt i32 %shl, -1
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp eq i32 %shl, -1
%mul = select i1 %cmp2, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a
br label %return
return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0
}
define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_op_b_0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmp w8, #0 // =0
; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
%shl = shl i32 %a, %b
%cmp = icmp sgt i32 %shl, 0
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp eq i32 %shl, 0
%mul = select i1 %cmp2, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a
br label %return
return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0
}
define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_op_b_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmp w8, #1 // =1
; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
%shl = shl i32 %a, %b
%cmp = icmp sgt i32 %shl, 1
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp eq i32 %shl, 1
%mul = select i1 %cmp2, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a
br label %return
return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0
}
define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_op_b_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmp w8, #2 // =2
; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
%shl = shl i32 %a, %b
%cmp = icmp sgt i32 %shl, 2
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp eq i32 %shl, 2
%mul = select i1 %cmp2, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a
br label %return
return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0
}
define i64 @i_a__2(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a__2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn w0, #2 // =2
; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, -2
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp1 = icmp eq i32 %a, -2
%mul = select i1 %cmp1, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a
br label %return
return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0
}
define i64 @i_a__1(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a__1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn w0, #1 // =1
; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: cmp w0, #0 // =0
; CHECK-NEXT: csel w8, w1, w8, ge
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, -1
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp1 = icmp eq i32 %a, -1
%mul = select i1 %cmp1, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a
br label %return
return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0
}
define i64 @i_a_0(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp w0, #0 // =0
; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp1 = icmp eq i32 %a, 0
%mul = select i1 %cmp1, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a
br label %return
return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0
}
define i64 @i_a_1(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp w0, #1 // =1
; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, 1
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp1 = icmp eq i32 %a, 1
%mul = select i1 %cmp1, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a
br label %return
return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0
}
define i64 @i_a_2(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp w0, #2 // =2
; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, 2
br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry
%cmp1 = icmp eq i32 %a, 2
%mul = select i1 %cmp1, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a
br label %return
return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0
}
|