1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
| ; RUN: llc -march=amdgcn -mcpu=gfx900 -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,GFX900
; RUN: llc -march=amdgcn -mcpu=gfx906 -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,GCN-DL-UNSAFE,GFX906-DL-UNSAFE
; RUN: llc -march=amdgcn -mcpu=gfx1011 -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,GCN-DL-UNSAFE,GFX10-DL-UNSAFE,GFX10-CONTRACT
; RUN: llc -march=amdgcn -mcpu=gfx1012 -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,GCN-DL-UNSAFE,GFX10-DL-UNSAFE,GFX10-CONTRACT
; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,GFX906
; RUN: llc -march=amdgcn -mcpu=gfx906 -mattr=-fp64-fp16-denormals,-fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,GFX906-CONTRACT
; RUN: llc -march=amdgcn -mcpu=gfx906 -mattr=+fp64-fp16-denormals,+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,GFX906-DENORM-CONTRACT
; (fadd (fmul S1.x, S2.x), (fadd (fmul (S1.y, S2.y), z))) -> (fdot2 S1, S2, z)
; Tests to make sure fdot2 is not generated when vector elements of dot-product expressions
; are not converted from f16 to f32.
; GCN-LABEL: {{^}}dotproduct_f16
; GFX900: v_fma_f16
; GFX900: v_fma_f16
; GFX906: v_mul_f16_e32
; GFX906: v_mul_f16_e32
; GFX906-DL-UNSAFE: v_fma_f16
; GFX10-CONTRACT: v_fmac_f16
; GFX906-CONTRACT: v_mac_f16_e32
; GFX906-DENORM-CONTRACT: v_fma_f16
define amdgpu_kernel void @dotproduct_f16(<2 x half> addrspace(1)* %src1,
<2 x half> addrspace(1)* %src2,
half addrspace(1)* nocapture %dst) {
entry:
%src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
%src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
%src1.el1 = extractelement <2 x half> %src1.vec, i64 0
%src2.el1 = extractelement <2 x half> %src2.vec, i64 0
%src1.el2 = extractelement <2 x half> %src1.vec, i64 1
%src2.el2 = extractelement <2 x half> %src2.vec, i64 1
%mul2 = fmul half %src1.el2, %src2.el2
%mul1 = fmul half %src1.el1, %src2.el1
%acc = load half, half addrspace(1)* %dst, align 2
%acc1 = fadd half %mul2, %acc
%acc2 = fadd half %mul1, %acc1
store half %acc2, half addrspace(1)* %dst, align 2
ret void
}
; We only want to generate fdot2 if vector element of dot product is converted from f16 to f32
; and the vectors are of type <2 x half>
; GCN-LABEL: {{^}}dotproduct_f16_f32
; GFX900: v_mad_mix_f32
; GFX900: v_mad_mix_f32
; GFX906: v_mad_f32
; GFX906: v_mac_f32_e32
; GFX906-DL-UNSAFE: v_dot2_f32_f16
; GFX10-DL-UNSAFE: v_dot2c_f32_f16_e32
; GFX906-CONTRACT: v_dot2_f32_f16
; GFX906-DENORM-CONTRACT: v_dot2_f32_f16
define amdgpu_kernel void @dotproduct_f16_f32(<2 x half> addrspace(1)* %src1,
<2 x half> addrspace(1)* %src2,
float addrspace(1)* nocapture %dst) {
entry:
%src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
%src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
%src1.el1 = extractelement <2 x half> %src1.vec, i64 0
%csrc1.el1 = fpext half %src1.el1 to float
%src2.el1 = extractelement <2 x half> %src2.vec, i64 0
%csrc2.el1 = fpext half %src2.el1 to float
%src1.el2 = extractelement <2 x half> %src1.vec, i64 1
%csrc1.el2 = fpext half %src1.el2 to float
%src2.el2 = extractelement <2 x half> %src2.vec, i64 1
%csrc2.el2 = fpext half %src2.el2 to float
%mul2 = fmul float %csrc1.el2, %csrc2.el2
%mul1 = fmul float %csrc1.el1, %csrc2.el1
%acc = load float, float addrspace(1)* %dst, align 4
%acc1 = fadd float %mul2, %acc
%acc2 = fadd float %mul1, %acc1
store float %acc2, float addrspace(1)* %dst, align 4
ret void
}
; We only want to generate fdot2 if vector element of dot product is converted from f16 to f32
; and the vectors are of type <2 x half>
; GCN-LABEL: {{^}}dotproduct_diffvecorder
; GFX900: v_mad_mix_f32
; GFX900: v_mad_mix_f32
; GFX906: v_mad_f32
; GFX906: v_mac_f32_e32
; GFX906-DL-UNSAFE: v_dot2_f32_f16
; GFX10-DL-UNSAFE: v_dot2c_f32_f16_e32
; GFX906-CONTRACT: v_dot2_f32_f16
; GFX906-DENORM-CONTRACT: v_dot2_f32_f16
define amdgpu_kernel void @dotproduct_diffvecorder(<2 x half> addrspace(1)* %src1,
<2 x half> addrspace(1)* %src2,
float addrspace(1)* nocapture %dst) {
entry:
%src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
%src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
%src1.el1 = extractelement <2 x half> %src1.vec, i64 0
%csrc1.el1 = fpext half %src1.el1 to float
%src2.el1 = extractelement <2 x half> %src2.vec, i64 0
%csrc2.el1 = fpext half %src2.el1 to float
%src1.el2 = extractelement <2 x half> %src1.vec, i64 1
%csrc1.el2 = fpext half %src1.el2 to float
%src2.el2 = extractelement <2 x half> %src2.vec, i64 1
%csrc2.el2 = fpext half %src2.el2 to float
%mul2 = fmul float %csrc2.el2, %csrc1.el2
%mul1 = fmul float %csrc1.el1, %csrc2.el1
%acc = load float, float addrspace(1)* %dst, align 4
%acc1 = fadd float %mul2, %acc
%acc2 = fadd float %mul1, %acc1
store float %acc2, float addrspace(1)* %dst, align 4
ret void
}
; Tests to make sure dot product is not generated when the vectors are not of <2 x half>.
; GCN-LABEL: {{^}}dotproduct_v4f16
; GFX900: v_mad_mix_f32
; GFX906: v_mad_f32
; GFX906: v_mac_f32_e32
; GCN-DL-UNSAFE: v_fma_mix_f32
; GFX906-CONTRACT: v_fma_mix_f32
; GFX906-DENORM-CONTRACT: v_fma_mix_f32
define amdgpu_kernel void @dotproduct_v4f16(<4 x half> addrspace(1)* %src1,
<4 x half> addrspace(1)* %src2,
float addrspace(1)* nocapture %dst) {
entry:
%src1.vec = load <4 x half>, <4 x half> addrspace(1)* %src1
%src2.vec = load <4 x half>, <4 x half> addrspace(1)* %src2
%src1.el1 = extractelement <4 x half> %src1.vec, i64 0
%csrc1.el1 = fpext half %src1.el1 to float
%src2.el1 = extractelement <4 x half> %src2.vec, i64 0
%csrc2.el1 = fpext half %src2.el1 to float
%src1.el2 = extractelement <4 x half> %src1.vec, i64 1
%csrc1.el2 = fpext half %src1.el2 to float
%src2.el2 = extractelement <4 x half> %src2.vec, i64 1
%csrc2.el2 = fpext half %src2.el2 to float
%mul2 = fmul float %csrc1.el2, %csrc2.el2
%mul1 = fmul float %csrc1.el1, %csrc2.el1
%acc = load float, float addrspace(1)* %dst, align 4
%acc1 = fadd float %mul2, %acc
%acc2 = fadd float %mul1, %acc1
store float %acc2, float addrspace(1)* %dst, align 4
ret void
}
; GCN-LABEL: {{^}}NotAdotproduct
; GFX900: v_mad_mix_f32
; GFX900: v_mad_mix_f32
; GFX906: v_mad_f32
; GFX906: v_mac_f32_e32
; GCN-DL-UNSAFE: v_fma_mix_f32
; GFX906-CONTRACT: v_fma_mix_f32
; GFX906-DENORM-CONTRACT: v_fma_mix_f32
define amdgpu_kernel void @NotAdotproduct(<2 x half> addrspace(1)* %src1,
<2 x half> addrspace(1)* %src2,
float addrspace(1)* nocapture %dst) {
entry:
%src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
%src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
%src1.el1 = extractelement <2 x half> %src1.vec, i64 0
%csrc1.el1 = fpext half %src1.el1 to float
%src2.el1 = extractelement <2 x half> %src2.vec, i64 0
%csrc2.el1 = fpext half %src2.el1 to float
%src1.el2 = extractelement <2 x half> %src1.vec, i64 1
%csrc1.el2 = fpext half %src1.el2 to float
%src2.el2 = extractelement <2 x half> %src2.vec, i64 1
%csrc2.el2 = fpext half %src2.el2 to float
%mul2 = fmul float %csrc1.el2, %csrc1.el1
%mul1 = fmul float %csrc2.el1, %csrc2.el2
%acc = load float, float addrspace(1)* %dst, align 4
%acc1 = fadd float %mul2, %acc
%acc2 = fadd float %mul1, %acc1
store float %acc2, float addrspace(1)* %dst, align 4
ret void
}
; GCN-LABEL: {{^}}Diff_Idx_NotAdotproduct
; GFX900: v_mad_mix_f32
; GFX900: v_mad_mix_f32
; GFX906: v_mad_f32
; GFX906: v_mac_f32_e32
; GCN-DL-UNSAFE: v_fma_mix_f32
; GFX906-CONTRACT: v_fma_mix_f32
; GFX906-DENORM-CONTRACT: v_fma_mix_f32
define amdgpu_kernel void @Diff_Idx_NotAdotproduct(<2 x half> addrspace(1)* %src1,
<2 x half> addrspace(1)* %src2,
float addrspace(1)* nocapture %dst) {
entry:
%src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
%src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
%src1.el1 = extractelement <2 x half> %src1.vec, i64 0
%csrc1.el1 = fpext half %src1.el1 to float
%src2.el1 = extractelement <2 x half> %src2.vec, i64 0
%csrc2.el1 = fpext half %src2.el1 to float
%src1.el2 = extractelement <2 x half> %src1.vec, i64 1
%csrc1.el2 = fpext half %src1.el2 to float
%src2.el2 = extractelement <2 x half> %src2.vec, i64 1
%csrc2.el2 = fpext half %src2.el2 to float
%mul2 = fmul float %csrc1.el2, %csrc2.el1
%mul1 = fmul float %csrc1.el1, %csrc2.el2
%acc = load float, float addrspace(1)* %dst, align 4
%acc1 = fadd float %mul2, %acc
%acc2 = fadd float %mul1, %acc1
store float %acc2, float addrspace(1)* %dst, align 4
ret void
}
|