reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

    1
    2
    3
    4
    5
    6
    7
    8
    9
   10
   11
   12
   13
   14
   15
   16
   17
   18
   19
   20
   21
   22
   23
   24
   25
   26
   27
   28
   29
   30
   31
   32
   33
   34
   35
   36
   37
   38
   39
   40
   41
   42
   43
   44
   45
   46
   47
   48
   49
   50
   51
   52
   53
   54
   55
   56
   57
   58
   59
   60
   61
   62
   63
   64
   65
   66
   67
   68
   69
   70
   71
   72
   73
   74
   75
   76
   77
   78
   79
   80
   81
   82
   83
   84
   85
   86
   87
   88
   89
   90
   91
   92
   93
   94
   95
   96
   97
   98
   99
  100
  101
  102
  103
  104
  105
  106
  107
  108
  109
  110
  111
  112
  113
  114
  115
  116
  117
  118
  119
  120
  121
  122
  123
  124
  125
  126
  127
  128
  129
  130
  131
  132
  133
  134
  135
  136
  137
  138
  139
  140
  141
  142
  143
  144
  145
  146
  147
  148
  149
  150
  151
  152
  153
  154

; RUN: llc < %s -march=mips -mcpu=mips32r6 -force-mips-long-branch | FileCheck %s

; Check that when MIPS32R6 with the static relocation model with the usage of
; long branches, that there is a nop between any compact branch and the static
; relocation method of expanding branches. Previously, it could result in 'j'
; following a b(ne|eq)zc, which would raise a reserved instruction exception.

declare i32 @f(i32)

declare i32 @g()

; CHECK-LABEL: test1:
; CHECK:       bnezc
; CHECK-NEXT:  nop

define i32 @test1(i32 %a) {
entry:
  %0 = icmp eq i32 %a, 0
  br i1 %0, label %cond.true, label %cond.false
cond.true:
  %1 = call i32 @f(i32 %a)
  ret i32 %1
cond.false:
  %2 = call i32 @g()
  ret i32 %2
}

; CHECK-LABEL: test2:
; CHECK:       bgezc
; CHECK-NEXT:  nop

define i32 @test2(i32 %a) {
entry:
  %0 = icmp sge i32 %a, 0
  br i1 %0, label %cond.true, label %cond.false
cond.true:
  %1 = call i32 @f(i32 %a)
  ret i32 %1
cond.false:
  %2 = call i32 @g()
  ret i32 %2
}

; CHECK-LABEL: test3:
; CHECK:       blezc
; CHECK-NEXT:  nop

define i32 @test3(i32 %a) {
entry:
  %0 = icmp sle i32 %a, 0
  br i1 %0, label %cond.true, label %cond.false
cond.true:
  %1 = call i32 @f(i32 %a)
  ret i32 %1
cond.false:
  %2 = call i32 @g()
  ret i32 %2
}

; CHECK-LABEL: test4:
; CHECK:       bgtzc
; CHECK-NEXT:  nop

define i32 @test4(i32 %a) {
entry:
  %0 = icmp sgt i32 %a, 0
  br i1 %0, label %cond.true, label %cond.false
cond.true:
  %1 = call i32 @f(i32 %a)
  ret i32 %1
cond.false:
  %2 = call i32 @g()
  ret i32 %2
}

; CHECK-LABEL: test5:
; CHECK:       bgezc
; CHECK-NEXT:  nop

define i32 @test5(i32 %a) {
entry:
  %0 = icmp slt i32 %a, 0
  br i1 %0, label %cond.true, label %cond.false
cond.true:
  %1 = call i32 @f(i32 %a)
  ret i32 %1
cond.false:
  %2 = call i32 @g()
  ret i32 %2
}

; CHECK-LABEL: test6:
; CHECK:       bnezc
; CHECK-NEXT:  nop

define i32 @test6(i32 %a, i32 %b) {
entry:
  %0 = icmp ugt i32 %a, %b
  br i1 %0, label %cond.true, label %cond.false
cond.true:
  %1 = call i32 @f(i32 %a)
  ret i32 %1
cond.false:
  %2 = call i32 @g()
  ret i32 %2
}

; CHECK-LABEL: test7:
; CHECK:       beqzc
; CHECK-NEXT:  nop

define i32 @test7(i32 %a, i32 %b) {
entry:
  %0 = icmp uge i32 %a, %b
  br i1 %0, label %cond.true, label %cond.false
cond.true:
  %1 = call i32 @f(i32 %a)
  ret i32 %1
cond.false:
  %2 = call i32 @g()
  ret i32 %2
}

; CHECK-LABEL: test8:
; CHECK:       bnezc
; CHECK-NEXT:  nop

define i32 @test8(i32 %a, i32 %b) {
entry:
  %0 = icmp ult i32 %a, %b
  br i1 %0, label %cond.true, label %cond.false
cond.true:
  %1 = call i32 @f(i32 %a)
  ret i32 %1
cond.false:
  %2 = call i32 @g()
  ret i32 %2
}

; CHECK-LABEL: test9:
; CHECK:       beqzc
; CHECK-NEXT:  nop

define i32 @test9(i32 %a, i32 %b) {
entry:
  %0 = icmp ule i32 %a, %b
  br i1 %0, label %cond.true, label %cond.false
cond.true:
  %1 = call i32 @f(i32 %a)
  ret i32 %1
cond.false:
  %2 = call i32 @g()
  ret i32 %2
}