1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i32 0, align 4
define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesi:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesi_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesi_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesi_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
|