1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE
@glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgeui:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgeui_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui_z(i32 zeroext %a) {
; CHECK-LABEL: test_llgeui_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_llgeui_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_llgeui_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_llgeui_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob
ret void
; CHECK_LABEL: test_igeuc_store:
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_llgeui_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_llgeui_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_z_store(i32 zeroext %a) {
; BE-LABEL: test_llgeui_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r3, r2, .LC0@toc@ha
; BE-NEXT: li r4, 1
; BE-NEXT: ld r3, .LC0@toc@l(r3)
; BE-NEXT: stw r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_llgeui_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r3, r2, glob@toc@ha
; LE-NEXT: li r4, 1
; LE-NEXT: stw r4, glob@toc@l(r3)
; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%sub = zext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_sext_z_store(i32 zeroext %a) {
; BE-LABEL: test_llgeui_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r3, r2, .LC0@toc@ha
; BE-NEXT: li r4, -1
; BE-NEXT: ld r3, .LC0@toc@l(r3)
; BE-NEXT: stw r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_llgeui_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r3, r2, glob@toc@ha
; LE-NEXT: li r4, -1
; LE-NEXT: stw r4, glob@toc@l(r3)
; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
}
|