1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
| ; Test load and zero rightmost byte.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
; Check LZRF with no displacement.
define i32 @f1(i32 *%src) {
; CHECK-LABEL: f1:
; CHECK: lzrf %r2, 0(%r2)
; CHECK: br %r14
%val = load i32, i32 *%src
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check the high end of the LZRF range.
define i32 @f2(i32 *%src) {
; CHECK-LABEL: f2:
; CHECK: lzrf %r2, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 131071
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f3(i32 *%src) {
; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: lzrf %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 131072
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check the high end of the negative LZRF range.
define i32 @f4(i32 *%src) {
; CHECK-LABEL: f4:
; CHECK: lzrf %r2, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -1
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check the low end of the LZRF range.
define i32 @f5(i32 *%src) {
; CHECK-LABEL: f5:
; CHECK: lzrf %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -131072
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 *%src) {
; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524292
; CHECK: lzrf %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -131073
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check that LZRF allows an index.
define i32 @f7(i64 %src, i64 %index) {
; CHECK-LABEL: f7:
; CHECK: lzrf %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524287
%ptr = inttoptr i64 %add2 to i32 *
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check LZRG with no displacement.
define i64 @f8(i64 *%src) {
; CHECK-LABEL: f8:
; CHECK: lzrg %r2, 0(%r2)
; CHECK: br %r14
%val = load i64, i64 *%src
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check the high end of the LZRG range.
define i64 @f9(i64 *%src) {
; CHECK-LABEL: f9:
; CHECK: lzrg %r2, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 65535
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f10(i64 *%src) {
; CHECK-LABEL: f10:
; CHECK: agfi %r2, 524288
; CHECK: lzrg %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 65536
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check the high end of the negative LZRG range.
define i64 @f11(i64 *%src) {
; CHECK-LABEL: f11:
; CHECK: lzrg %r2, -8(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 -1
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check the low end of the LZRG range.
define i64 @f12(i64 *%src) {
; CHECK-LABEL: f12:
; CHECK: lzrg %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 -65536
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f13(i64 *%src) {
; CHECK-LABEL: f13:
; CHECK: agfi %r2, -524296
; CHECK: lzrg %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 -65537
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check that LZRG allows an index.
define i64 @f14(i64 %src, i64 %index) {
; CHECK-LABEL: f14:
; CHECK: lzrg %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524287
%ptr = inttoptr i64 %add2 to i64 *
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check LLZRGF with no displacement.
define i64 @f15(i32 *%src) {
; CHECK-LABEL: f15:
; CHECK: llzrgf %r2, 0(%r2)
; CHECK: br %r14
%val = load i32, i32 *%src
%ext = zext i32 %val to i64
%and = and i64 %ext, 18446744073709551360
ret i64 %and
}
; ... and the other way around.
define i64 @f16(i32 *%src) {
; CHECK-LABEL: f16:
; CHECK: llzrgf %r2, 0(%r2)
; CHECK: br %r14
%val = load i32, i32 *%src
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check the high end of the LLZRGF range.
define i64 @f17(i32 *%src) {
; CHECK-LABEL: f17:
; CHECK: llzrgf %r2, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 131071
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f18(i32 *%src) {
; CHECK-LABEL: f18:
; CHECK: agfi %r2, 524288
; CHECK: llzrgf %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 131072
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check the high end of the negative LLZRGF range.
define i64 @f19(i32 *%src) {
; CHECK-LABEL: f19:
; CHECK: llzrgf %r2, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -1
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check the low end of the LLZRGF range.
define i64 @f20(i32 *%src) {
; CHECK-LABEL: f20:
; CHECK: llzrgf %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -131072
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f21(i32 *%src) {
; CHECK-LABEL: f21:
; CHECK: agfi %r2, -524292
; CHECK: llzrgf %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -131073
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check that LLZRGF allows an index.
define i64 @f22(i64 %src, i64 %index) {
; CHECK-LABEL: f22:
; CHECK: llzrgf %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524287
%ptr = inttoptr i64 %add2 to i32 *
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check that we still get a RISBGN if the source is in a register.
define i64 @f23(i32 %src) {
; CHECK-LABEL: f23:
; CHECK: risbgn %r2, %r2, 32, 183, 0
; CHECK: br %r14
%and = and i32 %src, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
|