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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
tools/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp 1394 carry = APSR_C;
1401 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1428 imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1584 m_new_inst_cpsr = m_opcode_cpsr;
1587 if (m_new_inst_cpsr != m_opcode_cpsr) {
1632 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1637 imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1725 Shift_C(value, shift_t, shift_n, APSR_C, carry, &success);
2097 if (m_opcode_cpsr != m_new_inst_cpsr)
3070 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry_out);
3272 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
3394 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
3520 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
3825 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
3896 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
5424 offset = Shift(Rm_data, shift_t, shift_n, APSR_C, &success);
5739 uint32_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
5857 AddWithCarryResult res = AddWithCarry(val1, imm32, APSR_C);
5941 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
5944 AddWithCarryResult res = AddWithCarry(val1, shifted, APSR_C);
6054 opcode, APSR_C,
6067 ARMExpandImm_C(opcode, APSR_C,
6168 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
6219 opcode, APSR_C,
6229 ARMExpandImm_C(opcode, APSR_C,
6332 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
6616 Shift(Rm, shift_t, shift_n, Bit32(m_opcode_cpsr, APSR_C), &success);
6616 Shift(Rm, shift_t, shift_n, Bit32(m_opcode_cpsr, APSR_C), &success);
7033 addr_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
7445 addr_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
7850 addr_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
8283 addr_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
8861 opcode, APSR_C,
8874 ARMExpandImm_C(opcode, APSR_C,
8980 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
9030 opcode, APSR_C,
9043 ARMExpandImm_C(opcode, APSR_C,
9145 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
9298 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
9359 AddWithCarryResult res = AddWithCarry(~reg_val, imm32, APSR_C);
9426 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
9429 AddWithCarryResult res = AddWithCarry(~val1, shifted, APSR_C);
9496 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, APSR_C);
9580 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
9583 AddWithCarryResult res = AddWithCarry(val1, ~shifted, APSR_C);
9786 opcode, APSR_C,
9794 ARMExpandImm_C(opcode, APSR_C,
9869 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
9911 opcode, APSR_C,
9919 ARMExpandImm_C(opcode, APSR_C,
10000 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
10087 uint32_t shifted = Shift(Rm, shift_t, shift_n, APSR_C, &success);
10173 uint32_t shifted = Shift(Rm, shift_t, shift_n, APSR_C, &success);
10305 uint32_t shifted = Shift(Rm, shift_t, shift_n, APSR_C, &success);
12748 operand2 = Shift(Rm, shift_t, shift_n, APSR_C, &success);
12790 result = AddWithCarry(Rn, operand2, APSR_C);
12795 result = AddWithCarry(Rn, ~(operand2), APSR_C);
12800 result = AddWithCarry(~(Rn), operand2, APSR_C);
13823 m_opcode_cpsr = CPSR_MODE_USR | MASK_CPSR_T;
13825 m_opcode_cpsr = CPSR_MODE_USR;
13833 m_opcode_cpsr = ReadRegisterUnsigned(eRegisterKindGeneric,
13844 if ((m_opcode_cpsr & MASK_CPSR_T) || m_arch.IsAlwaysThumbInstructions()) {
13868 uint32_t it = (Bits32(m_opcode_cpsr, 15, 10) << 2) |
13869 Bits32(m_opcode_cpsr, 26, 25);
13898 if (m_opcode_cpsr == 0)
13901 result = (m_opcode_cpsr & MASK_CPSR_Z) != 0;
13904 if (m_opcode_cpsr == 0)
13907 result = (m_opcode_cpsr & MASK_CPSR_C) != 0;
13910 if (m_opcode_cpsr == 0)
13913 result = (m_opcode_cpsr & MASK_CPSR_N) != 0;
13916 if (m_opcode_cpsr == 0)
13919 result = (m_opcode_cpsr & MASK_CPSR_V) != 0;
13922 if (m_opcode_cpsr == 0)
13925 result = ((m_opcode_cpsr & MASK_CPSR_C) != 0) &&
13926 ((m_opcode_cpsr & MASK_CPSR_Z) == 0);
13929 if (m_opcode_cpsr == 0)
13932 bool n = (m_opcode_cpsr & MASK_CPSR_N);
13933 bool v = (m_opcode_cpsr & MASK_CPSR_V);
13938 if (m_opcode_cpsr == 0)
13941 bool n = (m_opcode_cpsr & MASK_CPSR_N);
13942 bool v = (m_opcode_cpsr & MASK_CPSR_V);
13943 result = n == v && ((m_opcode_cpsr & MASK_CPSR_Z) == 0);
14022 uint32_t mode = Bits32(m_opcode_cpsr, 4, 0);
14037 uint32_t tmp_cpsr = Bits32(m_opcode_cpsr, 23, 20) << 20;
14066 m_opcode_cpsr = tmp_cpsr;
14144 m_new_inst_cpsr = m_opcode_cpsr;
14298 m_new_inst_cpsr = m_opcode_cpsr;
14305 if (m_new_inst_cpsr != m_opcode_cpsr) {
14328 if (m_opcode_cpsr == 0 || !m_ignore_conditions) {
14329 m_opcode_cpsr =