reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
420 ++numPhysicalOperands; 424 ++numPhysicalOperands; 463 HANDLE_OPERAND(relocation); 466 HANDLE_OPERAND(relocation); 469 HANDLE_OPERAND(relocation); 470 HANDLE_OPERAND(relocation); 474 assert(numPhysicalOperands <= 1 && 476 HANDLE_OPTIONAL(relocation) 480 HANDLE_OPERAND(relocation); 485 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 485 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 487 HANDLE_OPERAND(opcodeModifier) 488 HANDLE_OPTIONAL(relocation) 492 assert(numPhysicalOperands == 2 && 494 HANDLE_OPERAND(relocation) 495 HANDLE_OPERAND(opcodeModifier) 503 assert(numPhysicalOperands >= 2 + additionalOperands && 504 numPhysicalOperands <= 3 + additionalOperands && 507 HANDLE_OPERAND(rmRegister) 509 HANDLE_OPERAND(writemaskRegister) 514 HANDLE_OPERAND(vvvvRegister) 516 HANDLE_OPERAND(roRegister) 517 HANDLE_OPTIONAL(immediate) 524 assert(numPhysicalOperands >= 2 + additionalOperands && 525 numPhysicalOperands <= 3 + additionalOperands && 528 HANDLE_OPERAND(memory) 531 HANDLE_OPERAND(writemaskRegister) 536 HANDLE_OPERAND(vvvvRegister) 538 HANDLE_OPERAND(roRegister) 539 HANDLE_OPTIONAL(immediate) 548 assert(numPhysicalOperands >= 2 + additionalOperands && 549 numPhysicalOperands <= 4 + additionalOperands && 552 HANDLE_OPERAND(roRegister) 555 HANDLE_OPERAND(writemaskRegister) 560 HANDLE_OPERAND(vvvvRegister) 562 HANDLE_OPERAND(rmRegister) 563 HANDLE_OPTIONAL(immediate) 564 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 567 assert(numPhysicalOperands == 3 && 569 HANDLE_OPERAND(roRegister) 570 HANDLE_OPERAND(rmRegister) 571 HANDLE_OPERAND(vvvvRegister) 574 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 574 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 576 HANDLE_OPERAND(roRegister) 577 HANDLE_OPERAND(vvvvRegister) 578 HANDLE_OPERAND(immediate) // Register in imm[7:4] 579 HANDLE_OPERAND(rmRegister) 580 HANDLE_OPTIONAL(immediate) 583 assert(numPhysicalOperands == 3 && 585 HANDLE_OPERAND(roRegister) 586 HANDLE_OPERAND(rmRegister) 587 HANDLE_OPERAND(opcodeModifier) 595 assert(numPhysicalOperands >= 2 + additionalOperands && 596 numPhysicalOperands <= 4 + additionalOperands && 599 HANDLE_OPERAND(roRegister) 602 HANDLE_OPERAND(writemaskRegister) 607 HANDLE_OPERAND(vvvvRegister) 609 HANDLE_OPERAND(memory) 610 HANDLE_OPTIONAL(immediate) 611 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 614 assert(numPhysicalOperands == 3 && 616 HANDLE_OPERAND(roRegister) 617 HANDLE_OPERAND(memory) 618 HANDLE_OPERAND(vvvvRegister) 621 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 621 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 623 HANDLE_OPERAND(roRegister) 624 HANDLE_OPERAND(vvvvRegister) 625 HANDLE_OPERAND(immediate) // Register in imm[7:4] 626 HANDLE_OPERAND(memory) 627 HANDLE_OPTIONAL(immediate) 630 assert(numPhysicalOperands == 3 && 632 HANDLE_OPERAND(roRegister) 633 HANDLE_OPERAND(memory) 634 HANDLE_OPERAND(opcodeModifier) 637 assert(numPhysicalOperands == 2 && 639 HANDLE_OPERAND(rmRegister) 640 HANDLE_OPERAND(opcodeModifier) 654 assert(numPhysicalOperands >= 0 + additionalOperands && 655 numPhysicalOperands <= 3 + additionalOperands && 659 HANDLE_OPERAND(vvvvRegister) 662 HANDLE_OPERAND(writemaskRegister) 663 HANDLE_OPTIONAL(rmRegister) 664 HANDLE_OPTIONAL(relocation) 665 HANDLE_OPTIONAL(immediate) 668 assert(numPhysicalOperands == 2 && 670 HANDLE_OPERAND(memory) 671 HANDLE_OPERAND(opcodeModifier) 684 assert(numPhysicalOperands >= 1 + additionalOperands && 685 numPhysicalOperands <= 2 + additionalOperands && 689 HANDLE_OPERAND(vvvvRegister) 691 HANDLE_OPERAND(writemaskRegister) 692 HANDLE_OPERAND(memory) 693 HANDLE_OPTIONAL(relocation) 698 assert(numPhysicalOperands == 2 && 700 HANDLE_OPERAND(immediate) 701 HANDLE_OPERAND(immediate) 706 HANDLE_OPERAND(immediate) 707 HANDLE_OPERAND(immediate) 712 HANDLE_OPTIONAL(relocation)