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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc105736 /*236465*/ /*SwitchOpcode*/ 111, TARGET_VAL(ISD::FP_EXTEND),// ->236579
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4281 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc75299 /*166887*/ /*SwitchOpcode*/ 55, TARGET_VAL(ISD::FP_EXTEND),// ->166945
gen/lib/Target/ARM/ARMGenDAGISel.inc44872 /* 99257*/ /*SwitchOpcode*/ 88, TARGET_VAL(ISD::FP_EXTEND),// ->99348
gen/lib/Target/ARM/ARMGenFastISel.inc 2716 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68326 /*132291*/ /*SwitchOpcode*/ 8, TARGET_VAL(ISD::FP_EXTEND),// ->132302
gen/lib/Target/Mips/MipsGenDAGISel.inc27850 /* 52672*/ /*SwitchOpcode*/ 75, TARGET_VAL(ISD::FP_EXTEND),// ->52750
gen/lib/Target/Mips/MipsGenFastISel.inc 1202 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc71229 /*150209*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::FP_EXTEND),// ->150294
gen/lib/Target/PowerPC/PPCGenDAGISel.inc38880 /* 98253*/ /*SwitchOpcode*/ 114, TARGET_VAL(ISD::FP_EXTEND),// ->98370
39608 /* 99917*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
39620 /* 99937*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
39641 /* 99986*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
39653 /*100006*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1704 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13387 /* 25016*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::FP_EXTEND),// ->25029
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3019 /* 5584*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
3024 /* 5592*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
3037 /* 5614*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
3111 /* 5747*/ /*SwitchOpcode*/ 40, TARGET_VAL(ISD::FP_EXTEND),// ->5790
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc22480 /* 42274*/ OPC_SwitchOpcode /*2 cases */, 119, TARGET_VAL(ISD::FP_EXTEND),// ->42397
22547 /* 42416*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
22566 /* 42463*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
22639 /* 42627*/ /*SwitchOpcode*/ 83, TARGET_VAL(ISD::FP_EXTEND),// ->42713
22644 /* 42635*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
22662 /* 42674*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
22747 /* 42832*/ OPC_SwitchOpcode /*2 cases */, 113, TARGET_VAL(ISD::FP_EXTEND),// ->42949
22814 /* 42968*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
22833 /* 43012*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
22906 /* 43161*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::FP_EXTEND),// ->43245
22911 /* 43169*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
22928 /* 43207*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_EXTEND),
25286 /* 47979*/ /*SwitchOpcode*/ 86, TARGET_VAL(ISD::FP_EXTEND),// ->48068
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18866 /* 36019*/ /*SwitchOpcode*/ 8, TARGET_VAL(ISD::FP_EXTEND),// ->36030
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 969 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc71175 /*150129*/ /*SwitchOpcode*/ 23|128,2/*279*/, TARGET_VAL(ISD::FP_EXTEND),// ->150412
132852 /*272605*/ /*SwitchOpcode*/ 35, TARGET_VAL(ISD::FP_EXTEND),// ->272643
139449 /*286293*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FP_EXTEND),// ->286330
141976 /*291038*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::FP_EXTEND),// ->291058
144025 /*295034*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::FP_EXTEND),// ->295053
166620 /*337966*/ /*SwitchOpcode*/ 35, TARGET_VAL(ISD::FP_EXTEND),// ->338004
172932 /*351097*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FP_EXTEND),// ->351134
174959 /*354956*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::FP_EXTEND),// ->354976
176443 /*357892*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::FP_EXTEND),// ->357911
244109 /*498503*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FP_EXTEND),// ->498555
gen/lib/Target/X86/X86GenFastISel.inc 5915 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/TargetLowering.h 972 case ISD::STRICT_FP_EXTEND: EqOpc = ISD::FP_EXTEND; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1576 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
9239 CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND ||
11390 if (N0.getOpcode() == ISD::FP_EXTEND) {
11395 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11397 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11404 if (N1.getOpcode() == ISD::FP_EXTEND) {
11409 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11411 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11452 DAG.getNode(ISD::FP_EXTEND, SL, VT, U),
11453 DAG.getNode(ISD::FP_EXTEND, SL, VT, V),
11458 if (N02.getOpcode() == ISD::FP_EXTEND) {
11478 DAG.getNode(ISD::FP_EXTEND, SL, VT, X),
11479 DAG.getNode(ISD::FP_EXTEND, SL, VT, Y),
11481 DAG.getNode(ISD::FP_EXTEND, SL, VT, U),
11482 DAG.getNode(ISD::FP_EXTEND, SL, VT, V),
11485 if (N0.getOpcode() == ISD::FP_EXTEND) {
11502 if (N12.getOpcode() == ISD::FP_EXTEND) {
11518 if (N1.getOpcode() == ISD::FP_EXTEND) {
11610 if (N0.getOpcode() == ISD::FP_EXTEND) {
11615 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11617 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11626 if (N1.getOpcode() == ISD::FP_EXTEND) {
11632 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11634 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11646 if (N0.getOpcode() == ISD::FP_EXTEND) {
11654 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11656 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11671 if (N00.getOpcode() == ISD::FP_EXTEND) {
11677 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11679 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11722 if (N02.getOpcode() == ISD::FP_EXTEND) {
11729 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11731 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11745 if (N0.getOpcode() == ISD::FP_EXTEND) {
11752 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11754 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11757 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11759 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11770 N1.getOperand(2).getOpcode() == ISD::FP_EXTEND) {
11781 DAG.getNode(ISD::FP_EXTEND, SL,
11783 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11795 if (N1.getOpcode() == ISD::FP_EXTEND &&
11807 DAG.getNode(ISD::FP_EXTEND, SL, VT,
11809 DAG.getNode(ISD::FP_EXTEND, SL, VT, N101),
11812 DAG.getNode(ISD::FP_EXTEND, SL,
11814 DAG.getNode(ISD::FP_EXTEND, SL, VT,
12563 } else if (N1.getOpcode() == ISD::FP_EXTEND &&
12567 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV);
12652 if ((N1.getOpcode() == ISD::FP_EXTEND ||
13013 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
13069 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
13085 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2847 case ISD::FP_EXTEND:
3140 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
4288 ExtOp = ISD::FP_EXTEND;
4320 unsigned ExtOp = ISD::FP_EXTEND;
4333 unsigned ExtOp = ISD::FP_EXTEND;
4354 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4355 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4362 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4363 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4364 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4372 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4402 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 86 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break;
512 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op);
747 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL);
841 case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break;
1159 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break;
1408 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0));
1921 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break;
1973 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op);
2323 ISD::FP_EXTEND, DL, NVT,
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 429 case ISD::FP_EXTEND:
553 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 91 case ISD::FP_EXTEND:
720 ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res)
903 case ISD::FP_EXTEND:
2021 case ISD::FP_EXTEND:
2834 case ISD::FP_EXTEND:
4162 case ISD::FP_EXTEND:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 333 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND;
1100 ? getNode(ISD::FP_EXTEND, DL, VT, Op)
4030 case ISD::FP_EXTEND:
4382 case ISD::FP_EXTEND: {
4433 case ISD::FP_EXTEND:
4472 case ISD::FP_EXTEND:
7783 case ISD::STRICT_FP_EXTEND: NewOpc = ISD::FP_EXTEND; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 324 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
530 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
3420 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
6174 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 323 case ISD::FP_EXTEND: return "fp_extend";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 5353 if (!Op.hasOneUse() && !(Op.getOpcode() == ISD::FP_EXTEND &&
5448 case ISD::FP_EXTEND:
5565 case ISD::FP_EXTEND:
6489 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
lib/CodeGen/TargetLoweringBase.cpp 1625 case FPExt: return ISD::FP_EXTEND;
lib/Target/AArch64/AArch64ISelLowering.cpp 257 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
425 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
431 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
469 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
686 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
1611 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
1612 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
1712 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS);
1713 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS);
2450 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0)));
2466 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
2485 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
3018 case ISD::FP_EXTEND:
3899 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
4821 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
5035 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
5036 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
8168 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS);
8169 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS);
11831 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 2567 if (Src.getOpcode() == ISD::FP_EXTEND) {
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 2689 SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2712 SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
3773 case ISD::FP_EXTEND:
lib/Target/AMDGPU/SIISelLowering.cpp 274 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand);
569 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand);
2805 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
4234 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4235 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
4563 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) :
7617 SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
7618 SDValue CvtSrc1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
8744 case ISD::FP_EXTEND:
9710 Op1.getOpcode() != ISD::FP_EXTEND ||
9711 Op2.getOpcode() != ISD::FP_EXTEND)
9735 if (FMAOp1.getOpcode() != ISD::FP_EXTEND ||
9736 FMAOp2.getOpcode() != ISD::FP_EXTEND)
lib/Target/ARM/ARMISelLowering.cpp 857 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
970 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
976 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
9236 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16124 SrcVal = DAG.getNode(ISD::FP_EXTEND, Loc, MVT::f32, SrcVal);
16139 return DAG.getNode(ISD::FP_EXTEND, Loc, MVT::f64, SrcVal);
lib/Target/ARM/ARMTargetTransformInfo.cpp 157 { ISD::FP_EXTEND, MVT::v2f32, 2 },
158 { ISD::FP_EXTEND, MVT::v4f32, 4 }
162 ISD == ISD::FP_EXTEND)) {
lib/Target/Mips/MipsSEISelLowering.cpp 142 setOperationAction(ISD::FP_EXTEND, MVT::f16, Promote);
lib/Target/PowerPC/PPCISelLowering.cpp 887 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
919 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
960 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
7275 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
7278 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
7288 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
7297 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
7311 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
7314 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
7321 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
7327 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
7333 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
7339 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
7351 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
7415 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
10037 assert(Op.getOpcode() == ISD::FP_EXTEND &&
10163 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13091 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
13281 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
lib/Target/Sparc/SparcISelLowering.cpp 1716 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1744 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
3050 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
lib/Target/SystemZ/SystemZISelLowering.cpp 615 setTargetDAGCombine(ISD::FP_EXTEND);
5815 if (OtherExtend.getOpcode() == ISD::FP_EXTEND &&
6169 case ISD::FP_EXTEND: return combineFP_EXTEND(N, DCI);
lib/Target/X86/X86ISelDAGToDAG.cpp 990 case ISD::FP_EXTEND:
1010 if (N->getOpcode() == ISD::FP_EXTEND)
lib/Target/X86/X86ISelLowering.cpp 686 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
965 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
2546 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2681 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
19808 Sign = DAG.getNode(ISD::FP_EXTEND, dl, VT, Sign);
27704 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
28246 case ISD::FP_EXTEND: {
44718 if (InOpcode == ISD::FP_EXTEND &&
lib/Target/X86/X86IntrinsicsInfo.h 506 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
lib/Target/X86/X86TargetTransformInfo.cpp 1335 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 },
1336 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 },
1432 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 },
1513 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 },