reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

63562 /*121782*/  /*SwitchOpcode*/ 76|128,1/*204*/, TARGET_VAL(ISD::FSHR),// ->121990

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1537   case ISD::FSHR:               return visitFunnelShift(N);

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 1193     case ISD::FSHR:
 3322   case ISD::FSHR:

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 2960     Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0],
 2962     Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1],

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  382   case ISD::FSHR:
  809   case ISD::FSHR:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 2828   case ISD::FSHR:

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 6235     auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR;

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  245   case ISD::FSHR:                       return "fshr";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 1493   case ISD::FSHR: {
 7046   SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo,

lib/CodeGen/TargetLoweringBase.cpp

  648     setOperationAction(ISD::FSHR, VT, Expand);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1370   setOperationAction(ISD::FSHR, MVT::i32, Legal);
 1371   setOperationAction(ISD::FSHR, MVT::i64, Legal);

lib/Target/X86/X86ISelLowering.cpp

  213   for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
 1524         setOperationAction(ISD::FSHR, VT, Custom);
 1706       setOperationAction(ISD::FSHR, MVT::v32i16, Custom);
 1760         setOperationAction(ISD::FSHR, VT, Custom);
18252     Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt);
18279   assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) &&
18287   bool IsFSHR = Op.getOpcode() == ISD::FSHR;
27692   case ISD::FSHR:               return LowerFunnelShift(Op, Subtarget, DAG);
39700     Opc = ISD::FSHR;
39708     if (Opc == ISD::FSHR)