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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc113144 /*251950*/ /*SwitchOpcode*/ 76, TARGET_VAL(ISD::SMIN),// ->252029
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7739 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc54996 /*120396*/ /*SwitchOpcode*/ 97|128,9/*1249*/, TARGET_VAL(ISD::SMIN),// ->121649
55009 /*120422*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55058 /*120533*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55098 /*120628*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55141 /*120726*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55182 /*120823*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55252 /*120989*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55325 /*121160*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55341 /*121188*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55369 /*121239*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55400 /*121293*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55430 /*121346*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55481 /*121437*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55585 /*121657*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55592 /*121669*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55777 /*122089*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55846 /*122254*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
55908 /*122407*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
56025 /*122612*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
56075 /*122702*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
59887 /*130977*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::SMIN),// ->131041
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 7735 /* 29510*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::SMIN),// ->29617
gen/lib/Target/ARC/ARCGenDAGISel.inc 668 /* 1110*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SMIN),// ->1161
gen/lib/Target/ARM/ARMGenDAGISel.inc52617 /*117400*/ /*SwitchOpcode*/ 83|128,1/*211*/, TARGET_VAL(ISD::SMIN),// ->117615
gen/lib/Target/ARM/ARMGenFastISel.inc 5179 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenDAGISel.inc28532 /* 53949*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::SMIN),// ->54113
gen/lib/Target/Mips/MipsGenFastISel.inc 3422 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58310 /*123876*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::SMIN),// ->123960
gen/lib/Target/PowerPC/PPCGenDAGISel.inc42794 /*107300*/ /*SwitchOpcode*/ 74, TARGET_VAL(ISD::SMIN),// ->107377
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3250 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc78815 /*165654*/ /*SwitchOpcode*/ 117|128,1/*245*/, TARGET_VAL(ISD::SMIN),// ->165903
83873 /*175728*/ /*SwitchOpcode*/ 117|128,1/*245*/, TARGET_VAL(ISD::SMIN),// ->175977
88723 /*185260*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::SMIN),// ->185534
94989 /*197790*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::SMIN),// ->198060
101702 /*211158*/ /*SwitchOpcode*/ 56|128,2/*312*/, TARGET_VAL(ISD::SMIN),// ->211474
109036 /*225984*/ /*SwitchOpcode*/ 54|128,2/*310*/, TARGET_VAL(ISD::SMIN),// ->226298
115523 /*239034*/ /*SwitchOpcode*/ 52|128,2/*308*/, TARGET_VAL(ISD::SMIN),// ->239346
119107 /*245931*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::SMIN),// ->246095
121765 /*251219*/ /*SwitchOpcode*/ 126|128,1/*254*/, TARGET_VAL(ISD::SMIN),// ->251477
124454 /*256296*/ /*SwitchOpcode*/ 47, TARGET_VAL(ISD::SMIN),// ->256346
126877 /*260880*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SMIN),// ->260931
145654 /*298006*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMIN),
147570 /*301583*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SMIN),// ->301634
159546 /*324248*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SMIN),// ->324285
161276 /*327490*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SMIN),// ->327527
177366 /*359621*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::SMIN),// ->359643
178313 /*361319*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::SMIN),// ->361340
187320 /*378581*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SMIN),// ->378618
188087 /*380038*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SMIN),// ->380075
188730 /*381263*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::SMIN),// ->381285
189044 /*381840*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::SMIN),// ->381861
215434 /*437454*/ /*SwitchOpcode*/ 37|128,14/*1829*/, TARGET_VAL(ISD::SMIN),// ->439287
gen/lib/Target/X86/X86GenFastISel.inc13526 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h 2262 case ISD::SMIN:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1524 case ISD::SMIN:
4234 case ISD::SMIN: AltOpcode = ISD::UMIN; break;
4236 case ISD::UMIN: AltOpcode = ISD::SMIN; break;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3088 case ISD::SMIN:
3097 case ISD::SMIN: Pred = ISD::SETLT; break;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 79 case ISD::SMIN:
721 Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
1761 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
2085 case ISD::SMIN:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 435 case ISD::SMIN:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 120 case ISD::SMIN:
954 case ISD::SMIN:
2130 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break;
2744 case ISD::SMIN:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3270 case ISD::SMIN:
3277 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
3602 case ISD::SMIN:
3609 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
4708 case ISD::SMIN: return std::make_pair(C1.sle(C2) ? C1 : C2, true);
5107 case ISD::SMIN:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3291 case SPF_SMIN: Opc = ISD::SMIN; break;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 264 case ISD::SMIN: return "smin";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 7329 case ISD::VECREDUCE_SMIN: BaseOpcode = ISD::SMIN; break;
lib/CodeGen/TargetLoweringBase.cpp 642 setOperationAction(ISD::SMIN, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 877 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
2849 return DAG.getNode(ISD::SMIN, dl, Op.getValueType(),
12077 ReplaceReductionResults(N, Results, DAG, ISD::SMIN, AArch64ISD::SMINV);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 346 setOperationAction(ISD::SMIN, MVT::i32, Legal);
2641 B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,
lib/Target/AMDGPU/SIISelLowering.cpp 435 setOperationAction(ISD::SMIN, MVT::i16, Legal);
604 setOperationAction(ISD::SMIN, MVT::v2i16, Legal);
631 setOperationAction(ISD::SMIN, MVT::v4i16, Custom);
711 setTargetDAGCombine(ISD::SMIN);
4073 case ISD::SMIN:
9002 case ISD::SMIN:
9158 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
9289 case ISD::SMIN:
9958 case ISD::SMIN:
lib/Target/ARC/ARCISelLowering.cpp 98 setOperationAction(ISD::SMIN, MVT::i32, Legal);
lib/Target/ARM/ARMISelLowering.cpp 210 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
256 setOperationAction(ISD::SMIN, VT, Legal);
3732 ? ISD::SMIN : ISD::SMAX;
lib/Target/Mips/MipsSEISelLowering.cpp 345 setOperationAction(ISD::SMIN, Ty, Legal);
2033 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2045 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
lib/Target/NVPTX/NVPTXISelLowering.cpp 496 setOperationAction(ISD::SMIN, Ty, Legal);
lib/Target/PowerPC/PPCISelLowering.cpp 570 setOperationAction(ISD::SMIN, VT, Legal);
576 setOperationAction(ISD::SMIN, VT, Expand);
671 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
lib/Target/X86/X86ISelLowering.cpp 874 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
1043 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
1044 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
1207 setOperationAction(ISD::SMIN, MVT::v4i64, Custom);
1223 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1452 setOperationAction(ISD::SMIN, VT, Legal);
1546 setOperationAction(ISD::SMIN, VT, Legal);
1680 setOperationAction(ISD::SMIN, VT, Legal);
24999 Opcode = (Opcode == ISD::UMIN ? ISD::SMIN : ISD::SMAX);
25007 case ISD::SMIN: CC = ISD::CondCode::SETLT; break;
27771 case ISD::SMIN:
35758 Extract, BinOp, {ISD::SMAX, ISD::SMIN, ISD::UMAX, ISD::UMIN}, true);
35790 else if (BinOp == ISD::SMIN)
39903 if (SDValue SMin = MatchMinMax(In, ISD::SMIN, C2))
39909 if (SDValue SMin = MatchMinMax(SMax, ISD::SMIN, C2))
39950 if (SDValue SMin = MatchMinMax(In, ISD::SMIN, SignedMax))
39955 if (SDValue SMin = MatchMinMax(SMax, ISD::SMIN, SignedMax))
lib/Target/X86/X86TargetTransformInfo.cpp 2691 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
2707 {ISD::SMIN, MVT::v2i64, 6},
2709 {ISD::SMIN, MVT::v4i32, 6},
2711 {ISD::SMIN, MVT::v8i16, 4},
2713 {ISD::SMIN, MVT::v16i8, 8},
2719 {ISD::SMIN, MVT::v2i64, 9},
2721 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2723 {ISD::SMIN, MVT::v8i16, 2},
2725 {ISD::SMIN, MVT::v16i8, 3},
2730 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8"
2738 {ISD::SMIN, MVT::v2i64, 3},
2740 {ISD::SMIN, MVT::v4i32, 1},
2742 {ISD::SMIN, MVT::v8i16, 1},
2744 {ISD::SMIN, MVT::v16i8, 2},
2746 {ISD::SMIN, MVT::v4i64, 7},
2748 {ISD::SMIN, MVT::v8i32, 3},
2750 {ISD::SMIN, MVT::v16i16, 3},
2752 {ISD::SMIN, MVT::v32i8, 3},
2757 {ISD::SMIN, MVT::v4i64, 2},
2759 {ISD::SMIN, MVT::v8i32, 1},
2761 {ISD::SMIN, MVT::v16i16, 1},
2763 {ISD::SMIN, MVT::v32i8, 2},
2770 {ISD::SMIN, MVT::v8i64, 2},
2772 {ISD::SMIN, MVT::v16i32, 1},
2782 {ISD::SMIN, MVT::v2i64, 6},
2784 {ISD::SMIN, MVT::v4i32, 6},
2786 {ISD::SMIN, MVT::v8i16, 4},
2788 {ISD::SMIN, MVT::v16i8, 8},
2794 {ISD::SMIN, MVT::v2i64, 9},
2796 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2798 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5"
2800 {ISD::SMIN, MVT::v16i8, 3},
2805 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8"
2813 {ISD::SMIN, MVT::v2i64, 3},
2815 {ISD::SMIN, MVT::v4i32, 1},
2817 {ISD::SMIN, MVT::v8i16, 1},
2819 {ISD::SMIN, MVT::v16i8, 2},
2821 {ISD::SMIN, MVT::v4i64, 7},
2823 {ISD::SMIN, MVT::v8i32, 2},
2825 {ISD::SMIN, MVT::v16i16, 2},
2827 {ISD::SMIN, MVT::v32i8, 2},
2832 {ISD::SMIN, MVT::v4i64, 1},
2834 {ISD::SMIN, MVT::v8i32, 1},
2836 {ISD::SMIN, MVT::v16i16, 1},
2838 {ISD::SMIN, MVT::v32i8, 1},
2845 {ISD::SMIN, MVT::v8i64, 1},
2847 {ISD::SMIN, MVT::v16i32, 1},