reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/MachinePipeliner.cpp

 2650       if (SI.isAssignedRegDep())

lib/CodeGen/ScheduleDAG.cpp

   86     if (TRI && isAssignedRegDep())
  710     if (PredDep.isAssignedRegDep() &&

lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

  164     if (Pred.isAssignedRegDep()) {
  193     if (Succ.isAssignedRegDep()) {
  475     if (Pred.isAssignedRegDep()) {

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

  558     if (Pred.isAssignedRegDep()) {
  772     if (Succ.isAssignedRegDep() && LiveRegDefs[Succ.getReg()] == SU) {
  841     if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){
  887     if (Succ.isAssignedRegDep()) {
  901           if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg &&
 1356     if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU)
 2850       if (!SuccPred.isAssignedRegDep())
 3031       assert(!Edge.isAssignedRegDep());

lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp

  141     assert(!I->isAssignedRegDep() &&

lib/Target/Hexagon/HexagonHazardRecognizer.cpp

  144       if (S.isAssignedRegDep() && S.getLatency() == 0 &&
  159       if (S.isAssignedRegDep() && S.getLatency() == 0 &&

lib/Target/Hexagon/HexagonMachineScheduler.cpp

  707       if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() &&
  716       if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() &&

lib/Target/Hexagon/HexagonSubtarget.cpp

  421     if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
  460     if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
  476     if (I.isAssignedRegDep() && I.getLatency() == 0 &&

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

 1862         if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) ||