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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6849 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
6873 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
6876 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
6932 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
6933 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
6998 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
6999 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
7021 { 174, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #174 = CATCHRET
7022 { 175, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #175 = CLEANUPRET
7230 { 383, 1, 0, 4, 618, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #383 = B
7278 { 431, 1, 0, 4, 862, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #431 = BR
7301 { 454, 2, 0, 4, 623, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1ULL, ImplicitList1, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #454 = Bcc
7331 { 484, 2, 0, 4, 860, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #484 = CBNZW
7332 { 485, 2, 0, 4, 860, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #485 = CBNZX
7333 { 486, 2, 0, 4, 762, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #486 = CBZW
7334 { 487, 2, 0, 4, 762, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #487 = CBZX
7669 { 822, 0, 0, 4, 682, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #822 = DRPS
7734 { 887, 0, 0, 4, 685, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #887 = ERET
7735 { 888, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #888 = ERETAA
7736 { 889, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #889 = ERETAB
9858 { 3011, 1, 0, 4, 620, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #3011 = RET
9859 { 3012, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #3012 = RETAA
9860 { 3013, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #3013 = RETAB
9861 { 3014, 0, 0, 0, 622, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #3014 = RET_ReallyLR
11377 { 4530, 3, 0, 4, 861, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo430, -1 ,nullptr }, // Inst #4530 = TBNZW
11378 { 4531, 3, 0, 4, 861, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #4531 = TBNZX
11391 { 4544, 3, 0, 4, 621, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo430, -1 ,nullptr }, // Inst #4544 = TBZW
11392 { 4545, 3, 0, 4, 621, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #4545 = TBZX
11395 { 4548, 2, 0, 0, 619, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #4548 = TCRETURNdi
11396 { 4549, 2, 0, 0, 622, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo439, -1 ,nullptr }, // Inst #4549 = TCRETURNri
11397 { 4550, 2, 0, 0, 11, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #4550 = TCRETURNriALL
11398 { 4551, 2, 0, 0, 11, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo440, -1 ,nullptr }, // Inst #4551 = TCRETURNriBTI
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16064 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
16088 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
16091 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
16147 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
16148 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
16213 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
16214 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
17655 { 1593, 1, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #1593 = SI_BR_UNDEF
17658 { 1596, 4, 1, 12, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo146, -1 ,nullptr }, // Inst #1596 = SI_ELSE
17660 { 1598, 3, 1, 12, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo148, -1 ,nullptr }, // Inst #1598 = SI_IF
17678 { 1616, 3, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList11, OperandInfo162, -1 ,nullptr }, // Inst #1616 = SI_KILL_F32_COND_IMM_TERMINATOR
17680 { 1618, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList11, OperandInfo163, -1 ,nullptr }, // Inst #1618 = SI_KILL_I1_TERMINATOR
17681 { 1619, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo164, -1 ,nullptr }, // Inst #1619 = SI_LOOP
17683 { 1621, 1, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000002ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1621 = SI_MASK_BRANCH
17684 { 1622, 2, 0, 12, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo164, -1 ,nullptr }, // Inst #1622 = SI_NON_UNIFORM_BRCOND_PSEUDO
17687 { 1625, 0, 0, 0, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1625 = SI_RETURN
17688 { 1626, 0, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x11000000001ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1626 = SI_RETURN_TO_EPILOG
17731 { 1669, 3, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Convergent), 0x1ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1669 = SI_TCRETURN
17746 { 1684, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1684 = S_ANDN2_B32_term
17748 { 1686, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #1686 = S_ANDN2_B64_term
18076 { 2014, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2014 = S_MOV_B32_term
18078 { 2016, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2016 = S_MOV_B64_term
18102 { 2040, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2040 = S_OR_B32_term
18125 { 2063, 1, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2063 = S_SETPC_B64
18126 { 2064, 1, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2064 = S_SETPC_B64_return
18139 { 2077, 2, 0, 0, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x21ULL, ImplicitList2, ImplicitList2, OperandInfo261, -1 ,nullptr }, // Inst #2077 = S_SUBVECTOR_LOOP_BEGIN
18140 { 2078, 2, 0, 0, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x21ULL, ImplicitList2, ImplicitList2, OperandInfo261, -1 ,nullptr }, // Inst #2078 = S_SUBVECTOR_LOOP_END
18158 { 2096, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2096 = S_XOR_B32_term
18160 { 2098, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2098 = S_XOR_B64_term
27056 { 10994, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #10994 = S_BRANCH
27057 { 10995, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #10995 = S_BRANCH_pad_s_nop
27321 { 11259, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11259 = S_CBRANCH_CDBGSYS
27322 { 11260, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11260 = S_CBRANCH_CDBGSYS_AND_USER
27323 { 11261, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11261 = S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop
27324 { 11262, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11262 = S_CBRANCH_CDBGSYS_OR_USER
27325 { 11263, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11263 = S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop
27326 { 11264, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11264 = S_CBRANCH_CDBGSYS_pad_s_nop
27327 { 11265, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11265 = S_CBRANCH_CDBGUSER
27328 { 11266, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11266 = S_CBRANCH_CDBGUSER_pad_s_nop
27329 { 11267, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList2, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11267 = S_CBRANCH_EXECNZ
27330 { 11268, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList2, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11268 = S_CBRANCH_EXECNZ_pad_s_nop
27331 { 11269, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList2, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11269 = S_CBRANCH_EXECZ
27332 { 11270, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList2, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11270 = S_CBRANCH_EXECZ_pad_s_nop
27339 { 11277, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11277 = S_CBRANCH_SCC0
27340 { 11278, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11278 = S_CBRANCH_SCC0_pad_s_nop
27341 { 11279, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11279 = S_CBRANCH_SCC1
27342 { 11280, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11280 = S_CBRANCH_SCC1_pad_s_nop
27343 { 11281, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11281 = S_CBRANCH_VCCNZ
27344 { 11282, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11282 = S_CBRANCH_VCCNZ_pad_s_nop
27345 { 11283, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11283 = S_CBRANCH_VCCZ
27346 { 11284, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList14, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11284 = S_CBRANCH_VCCZ_pad_s_nop
27407 { 11345, 0, 0, 4, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #11345 = S_CODE_END
27432 { 11370, 1, 0, 4, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #11370 = S_ENDPGM
27433 { 11371, 0, 0, 4, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #11371 = S_ENDPGM_ORDERED_PS_DONE
27434 { 11372, 0, 0, 4, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #11372 = S_ENDPGM_SAVED
gen/lib/Target/AMDGPU/R600GenInstrInfo.inc 640 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
664 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
667 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
723 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
724 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
789 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
790 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
812 { 174, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #174 = BRANCH
813 { 175, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #175 = BRANCH_COND_f32
814 { 176, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #176 = BRANCH_COND_i32
815 { 177, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #177 = BREAK
816 { 178, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #178 = BREAKC_f32
817 { 179, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #179 = BREAKC_i32
818 { 180, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #180 = BREAK_LOGICALNZ_f32
819 { 181, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #181 = BREAK_LOGICALNZ_i32
820 { 182, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #182 = BREAK_LOGICALZ_f32
821 { 183, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #183 = BREAK_LOGICALZ_i32
823 { 185, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #185 = CONTINUE
824 { 186, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #186 = CONTINUEC_f32
825 { 187, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #187 = CONTINUEC_i32
826 { 188, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #188 = CONTINUE_LOGICALNZ_f32
827 { 189, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #189 = CONTINUE_LOGICALNZ_i32
828 { 190, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #190 = CONTINUE_LOGICALZ_f32
829 { 191, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #191 = CONTINUE_LOGICALZ_i32
832 { 194, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #194 = DEFAULT
835 { 197, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #197 = ELSE
836 { 198, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #198 = END
837 { 199, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #199 = ENDFUNC
838 { 200, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #200 = ENDIF
839 { 201, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #201 = ENDLOOP
840 { 202, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #202 = ENDMAIN
841 { 203, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #203 = ENDSWITCH
844 { 206, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #206 = FUNC
845 { 207, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #207 = IFC_f32
846 { 208, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #208 = IFC_i32
847 { 209, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #209 = IF_LOGICALNZ_f32
848 { 210, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #210 = IF_LOGICALNZ_i32
849 { 211, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #211 = IF_LOGICALZ_f32
850 { 212, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #212 = IF_LOGICALZ_i32
852 { 214, 1, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #214 = JUMP
853 { 215, 2, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #215 = JUMP_COND
865 { 227, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #227 = RETDYN
866 { 228, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #228 = RETURN
869 { 231, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #231 = WHILELOOP
gen/lib/Target/ARC/ARCGenInstrInfo.inc 645 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
669 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
672 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
728 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
729 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
794 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
795 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
819 { 176, 4, 0, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #176 = BRcc_rr_p
820 { 177, 4, 0, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #177 = BRcc_ru6_p
883 { 240, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #240 = BR
886 { 243, 4, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #243 = BRcc_rr
887 { 244, 4, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #244 = BRcc_ru6
891 { 248, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #248 = Bcc
918 { 275, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #275 = GEN_JEQ_S
921 { 278, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #278 = GEN_JNE_S
924 { 281, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #281 = GEN_J_S_D_BLINK
947 { 304, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #304 = J
951 { 308, 1, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #308 = J_LImm
952 { 309, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #309 = J_S_BLINK
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5835 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
5859 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
5862 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
5918 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
5919 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
5984 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
5985 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
6016 { 183, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #183 = B
6017 { 184, 4, 0, 0, 858, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #184 = BCCZi64
6018 { 185, 6, 0, 0, 858, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #185 = BCCi64
6022 { 189, 3, 0, 4, 859, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #189 = BR_JTadd
6023 { 190, 3, 0, 4, 862, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #190 = BR_JTm_i12
6024 { 191, 4, 0, 4, 862, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #191 = BR_JTm_rs
6025 { 192, 2, 0, 4, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #192 = BR_JTr
6036 { 203, 2, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo36, -1 ,nullptr }, // Inst #203 = Int_eh_sjlj_longjmp
6044 { 211, 5, 1, 4, 419, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #211 = LDMIA_RET
6065 { 232, 1, 0, 4, 880, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #232 = MOVPCRX
6113 { 280, 3, 0, 4, 850, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #280 = SUBS_PC_LR
6118 { 285, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #285 = TAILJMPd
6119 { 286, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #286 = TAILJMPr
6120 { 287, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #287 = TAILJMPr4
6121 { 288, 1, 0, 0, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #288 = TCRETURNdi
6122 { 289, 1, 0, 0, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #289 = TCRETURNri
6352 { 519, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #519 = t2BF_LabelPseudo
6353 { 520, 3, 0, 4, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #520 = t2BR_JT
6355 { 522, 5, 1, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #522 = t2LDMIA_RET
6366 { 533, 2, 0, 8, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #533 = t2LoopEnd
6392 { 559, 4, 0, 4, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #559 = t2TBB_JT
6393 { 560, 4, 0, 4, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #560 = t2TBH_JT
6394 { 561, 2, 0, 8, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo109, -1 ,nullptr }, // Inst #561 = t2WhileLoopStart
6403 { 570, 3, 0, 2, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #570 = tBRIND
6404 { 571, 2, 0, 2, 859, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #571 = tBR_JTr
6406 { 573, 2, 0, 2, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #573 = tBX_RET
6407 { 574, 3, 0, 2, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #574 = tBX_RET_vararg
6408 { 575, 3, 0, 4, 853, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo118, -1 ,nullptr }, // Inst #575 = tBfar
6419 { 586, 3, 0, 2, 420, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #586 = tPOP_RET
6425 { 592, 3, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #592 = tTAILJMPd
6426 { 593, 3, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #593 = tTAILJMPdND
6427 { 594, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #594 = tTAILJMPr
6428 { 595, 4, 0, 2, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #595 = tTBB_JT
6429 { 596, 4, 0, 2, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #596 = tTBH_JT
6460 { 627, 1, 0, 4, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #627 = BX
6462 { 629, 2, 0, 4, 851, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #629 = BX_RET
6463 { 630, 3, 0, 4, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #630 = BX_pred
6464 { 631, 3, 0, 4, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #631 = Bcc
6493 { 660, 2, 0, 4, 841, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, ImplicitList10, OperandInfo116, -1 ,nullptr }, // Inst #660 = ERET
6584 { 751, 2, 0, 4, 880, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #751 = MOVPCLR
6605 { 772, 2, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #772 = MVE_DLSTP_16
6606 { 773, 2, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #773 = MVE_DLSTP_32
6607 { 774, 2, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #774 = MVE_DLSTP_64
6608 { 775, 2, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #775 = MVE_DLSTP_8
6609 { 776, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #776 = MVE_LCTP
6610 { 777, 3, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #777 = MVE_LETP
7454 { 1621, 3, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1621 = MVE_WLSTP_16
7455 { 1622, 3, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1622 = MVE_WLSTP_32
7456 { 1623, 3, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1623 = MVE_WLSTP_64
7457 { 1624, 3, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1624 = MVE_WLSTP_8
7667 { 1834, 0, 0, 4, 841, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1834 = TRAP
7668 { 1835, 0, 0, 4, 841, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1835 = TRAPNaCl
9585 { 3752, 3, 0, 4, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #3752 = t2B
9596 { 3763, 3, 0, 4, 861, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #3763 = t2BXJ
9597 { 3764, 3, 0, 4, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #3764 = t2Bcc
9707 { 3874, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #3874 = t2LE
9708 { 3875, 3, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #3875 = t2LEUpdate
9773 { 3940, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3940 = t2RFEDB
9774 { 3941, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3941 = t2RFEDBW
9775 { 3942, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3942 = t2RFEIA
9776 { 3943, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3943 = t2RFEIAW
9899 { 4066, 3, 0, 4, 849, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, ImplicitList10, OperandInfo142, -1 ,nullptr }, // Inst #4066 = t2SUBS_PC_LR
9910 { 4077, 4, 0, 4, 859, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo495, -1 ,nullptr }, // Inst #4077 = t2TBB
9911 { 4078, 4, 0, 4, 859, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo495, -1 ,nullptr }, // Inst #4078 = t2TBH
9957 { 4124, 3, 1, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #4124 = t2WLS
9971 { 4138, 3, 0, 2, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #4138 = tB
9978 { 4145, 3, 0, 2, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #4145 = tBX
9979 { 4146, 3, 0, 2, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #4146 = tBXNS
9980 { 4147, 3, 0, 2, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #4147 = tBcc
9981 { 4148, 2, 0, 2, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo509, -1 ,nullptr }, // Inst #4148 = tCBNZ
9982 { 4149, 2, 0, 2, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo509, -1 ,nullptr }, // Inst #4149 = tCBZ
9991 { 4158, 2, 0, 0, 849, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo36, -1 ,nullptr }, // Inst #4158 = tInt_WIN_eh_sjlj_longjmp
9992 { 4159, 2, 0, 0, 1028, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo126, -1 ,nullptr }, // Inst #4159 = tInt_eh_sjlj_longjmp
10040 { 4207, 0, 0, 2, 842, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #4207 = tTRAP
10045 { 4212, 0, 0, 2, 843, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #4212 = t__brkdiv0
gen/lib/Target/AVR/AVRGenInstrInfo.inc 485 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
509 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
512 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
568 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
569 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
634 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
635 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
738 { 255, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #255 = BRBCsk
739 { 256, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #256 = BRBSsk
741 { 258, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #258 = BREQk
742 { 259, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #259 = BRGEk
743 { 260, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #260 = BRLOk
744 { 261, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #261 = BRLTk
745 { 262, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #262 = BRMIk
746 { 263, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #263 = BRNEk
747 { 264, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #264 = BRPLk
748 { 265, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #265 = BRSHk
757 { 274, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #274 = CPSE
761 { 278, 0, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList4, nullptr, nullptr, -1 ,nullptr }, // Inst #278 = EIJMP
770 { 287, 0, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList4, nullptr, nullptr, -1 ,nullptr }, // Inst #287 = IJMP
773 { 290, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #290 = JMPk
800 { 317, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #317 = RET
801 { 318, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #318 = RETI
802 { 319, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #319 = RJMPk
807 { 324, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #324 = SBICAb
808 { 325, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #325 = SBISAb
810 { 327, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #327 = SBRCRrB
811 { 328, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #328 = SBRSRrB
gen/lib/Target/BPF/BPFGenInstrInfo.inc 422 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
446 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
449 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
505 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
506 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
571 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
572 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
623 { 203, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #203 = JEQ_ri
624 { 204, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #204 = JEQ_ri_32
625 { 205, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #205 = JEQ_rr
626 { 206, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #206 = JEQ_rr_32
627 { 207, 1, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #207 = JMP
628 { 208, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #208 = JNE_ri
629 { 209, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #209 = JNE_ri_32
630 { 210, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #210 = JNE_rr
631 { 211, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #211 = JNE_rr_32
632 { 212, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #212 = JSGE_ri
633 { 213, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #213 = JSGE_ri_32
634 { 214, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #214 = JSGE_rr
635 { 215, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #215 = JSGE_rr_32
636 { 216, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #216 = JSGT_ri
637 { 217, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #217 = JSGT_ri_32
638 { 218, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #218 = JSGT_rr
639 { 219, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #219 = JSGT_rr_32
640 { 220, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #220 = JSLE_ri
641 { 221, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #221 = JSLE_ri_32
642 { 222, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #222 = JSLE_rr
643 { 223, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #223 = JSLE_rr_32
644 { 224, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #224 = JSLT_ri
645 { 225, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #225 = JSLT_ri_32
646 { 226, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #226 = JSLT_rr
647 { 227, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #227 = JSLT_rr_32
648 { 228, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #228 = JUGE_ri
649 { 229, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #229 = JUGE_ri_32
650 { 230, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #230 = JUGE_rr
651 { 231, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #231 = JUGE_rr_32
652 { 232, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #232 = JUGT_ri
653 { 233, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #233 = JUGT_ri_32
654 { 234, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #234 = JUGT_rr
655 { 235, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #235 = JUGT_rr_32
656 { 236, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #236 = JULE_ri
657 { 237, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #237 = JULE_ri_32
658 { 238, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #238 = JULE_rr
659 { 239, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #239 = JULE_rr_32
660 { 240, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #240 = JULT_ri
661 { 241, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #241 = JULT_ri_32
662 { 242, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #242 = JULT_rr
663 { 243, 3, 0, 8, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #243 = JULT_rr_32
698 { 278, 0, 0, 8, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #278 = RET
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3632 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
3656 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
3659 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
3715 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
3716 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
3781 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
3782 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
3830 { 200, 1, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList5, ImplicitList6, OperandInfo2, -1 ,nullptr }, // Inst #200 = ENDLOOP0
3831 { 201, 1, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList7, ImplicitList8, OperandInfo2, -1 ,nullptr }, // Inst #201 = ENDLOOP01
3832 { 202, 1, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList9, ImplicitList10, OperandInfo2, -1 ,nullptr }, // Inst #202 = ENDLOOP1
3833 { 203, 0, 0, 4, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x24ULL, ImplicitList11, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #203 = J2_endloop0
3835 { 205, 0, 0, 4, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x24ULL, ImplicitList15, ImplicitList16, nullptr, -1 ,nullptr }, // Inst #205 = J2_endloop1
3948 { 318, 1, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x29ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #318 = PS_tailcall_i
3949 { 319, 1, 0, 4, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, ImplicitList19, OperandInfo71, -1 ,nullptr }, // Inst #319 = PS_tailcall_r
4707 { 1077, 1, 0, 4, 38, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000024ULL, ImplicitList22, ImplicitList19, OperandInfo71, -1 ,nullptr }, // Inst #1077 = EH_RETURN_JMPR
4776 { 1146, 1, 0, 4, 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x5b10800024ULL, nullptr, ImplicitList19, OperandInfo2, -1 ,nullptr }, // Inst #1146 = J2_jump
4777 { 1147, 2, 0, 4, 15, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32800c24ULL, nullptr, ImplicitList19, OperandInfo48, -1 ,nullptr }, // Inst #1147 = J2_jumpf
4778 { 1148, 2, 0, 4, 106, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32801c24ULL, nullptr, ImplicitList19, OperandInfo48, -1 ,nullptr }, // Inst #1148 = J2_jumpfnew
4779 { 1149, 2, 0, 4, 106, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007a32801c24ULL, nullptr, ImplicitList19, OperandInfo48, -1 ,nullptr }, // Inst #1149 = J2_jumpfnewpt
4780 { 1150, 2, 0, 4, 107, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007a32800c24ULL, nullptr, ImplicitList19, OperandInfo48, -1 ,nullptr }, // Inst #1150 = J2_jumpfpt
4781 { 1151, 1, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, ImplicitList19, OperandInfo71, -1 ,nullptr }, // Inst #1151 = J2_jumpr
4782 { 1152, 2, 0, 4, 16, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1152 = J2_jumprf
4783 { 1153, 2, 0, 4, 108, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1153 = J2_jumprfnew
4784 { 1154, 2, 0, 4, 108, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x2001000001c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1154 = J2_jumprfnewpt
4785 { 1155, 2, 0, 4, 109, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x2001000000c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1155 = J2_jumprfpt
4786 { 1156, 2, 0, 4, 110, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001406ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1156 = J2_jumprgtez
4787 { 1157, 2, 0, 4, 110, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007000001406ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1157 = J2_jumprgtezpt
4788 { 1158, 2, 0, 4, 110, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001406ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1158 = J2_jumprltez
4789 { 1159, 2, 0, 4, 110, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007000001406ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1159 = J2_jumprltezpt
4790 { 1160, 2, 0, 4, 110, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001406ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1160 = J2_jumprnz
4791 { 1161, 2, 0, 4, 110, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007000001406ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1161 = J2_jumprnzpt
4792 { 1162, 2, 0, 4, 16, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1162 = J2_jumprt
4793 { 1163, 2, 0, 4, 108, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1163 = J2_jumprtnew
4794 { 1164, 2, 0, 4, 108, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x2001000001424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1164 = J2_jumprtnewpt
4795 { 1165, 2, 0, 4, 109, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x2001000000424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1165 = J2_jumprtpt
4796 { 1166, 2, 0, 4, 110, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001406ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1166 = J2_jumprz
4797 { 1167, 2, 0, 4, 110, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007000001406ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1167 = J2_jumprzpt
4798 { 1168, 2, 0, 4, 15, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32800424ULL, nullptr, ImplicitList19, OperandInfo48, -1 ,nullptr }, // Inst #1168 = J2_jumpt
4799 { 1169, 2, 0, 4, 106, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32801424ULL, nullptr, ImplicitList19, OperandInfo48, -1 ,nullptr }, // Inst #1169 = J2_jumptnew
4800 { 1170, 2, 0, 4, 106, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007a32801424ULL, nullptr, ImplicitList19, OperandInfo48, -1 ,nullptr }, // Inst #1170 = J2_jumptnewpt
4801 { 1171, 2, 0, 4, 107, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007a32800424ULL, nullptr, ImplicitList19, OperandInfo48, -1 ,nullptr }, // Inst #1171 = J2_jumptpt
4819 { 1189, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c28ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1189 = J4_cmpeq_f_jumpnv_nt
4820 { 1190, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804c28ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1190 = J4_cmpeq_f_jumpnv_t
4821 { 1191, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1191 = J4_cmpeq_fp0_jump_nt
4822 { 1192, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1192 = J4_cmpeq_fp0_jump_t
4823 { 1193, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1193 = J4_cmpeq_fp1_jump_nt
4824 { 1194, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1194 = J4_cmpeq_fp1_jump_t
4825 { 1195, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804428ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1195 = J4_cmpeq_t_jumpnv_nt
4826 { 1196, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804428ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1196 = J4_cmpeq_t_jumpnv_t
4827 { 1197, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1197 = J4_cmpeq_tp0_jump_nt
4828 { 1198, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1198 = J4_cmpeq_tp0_jump_t
4829 { 1199, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1199 = J4_cmpeq_tp1_jump_nt
4830 { 1200, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1200 = J4_cmpeq_tp1_jump_t
4831 { 1201, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c28ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1201 = J4_cmpeqi_f_jumpnv_nt
4832 { 1202, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804c28ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1202 = J4_cmpeqi_f_jumpnv_t
4833 { 1203, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1203 = J4_cmpeqi_fp0_jump_nt
4834 { 1204, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1204 = J4_cmpeqi_fp0_jump_t
4835 { 1205, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1205 = J4_cmpeqi_fp1_jump_nt
4836 { 1206, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1206 = J4_cmpeqi_fp1_jump_t
4837 { 1207, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804428ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1207 = J4_cmpeqi_t_jumpnv_nt
4838 { 1208, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804428ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1208 = J4_cmpeqi_t_jumpnv_t
4839 { 1209, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1209 = J4_cmpeqi_tp0_jump_nt
4840 { 1210, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1210 = J4_cmpeqi_tp0_jump_t
4841 { 1211, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1211 = J4_cmpeqi_tp1_jump_nt
4842 { 1212, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1212 = J4_cmpeqi_tp1_jump_t
4843 { 1213, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c28ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1213 = J4_cmpeqn1_f_jumpnv_nt
4844 { 1214, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804c28ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1214 = J4_cmpeqn1_f_jumpnv_t
4845 { 1215, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1215 = J4_cmpeqn1_fp0_jump_nt
4846 { 1216, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1216 = J4_cmpeqn1_fp0_jump_t
4847 { 1217, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1217 = J4_cmpeqn1_fp1_jump_nt
4848 { 1218, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1218 = J4_cmpeqn1_fp1_jump_t
4849 { 1219, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804428ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1219 = J4_cmpeqn1_t_jumpnv_nt
4850 { 1220, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804428ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1220 = J4_cmpeqn1_t_jumpnv_t
4851 { 1221, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1221 = J4_cmpeqn1_tp0_jump_nt
4852 { 1222, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1222 = J4_cmpeqn1_tp0_jump_t
4853 { 1223, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1223 = J4_cmpeqn1_tp1_jump_nt
4854 { 1224, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1224 = J4_cmpeqn1_tp1_jump_t
4855 { 1225, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c28ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1225 = J4_cmpgt_f_jumpnv_nt
4856 { 1226, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804c28ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1226 = J4_cmpgt_f_jumpnv_t
4857 { 1227, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1227 = J4_cmpgt_fp0_jump_nt
4858 { 1228, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1228 = J4_cmpgt_fp0_jump_t
4859 { 1229, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1229 = J4_cmpgt_fp1_jump_nt
4860 { 1230, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1230 = J4_cmpgt_fp1_jump_t
4861 { 1231, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804428ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1231 = J4_cmpgt_t_jumpnv_nt
4862 { 1232, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804428ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1232 = J4_cmpgt_t_jumpnv_t
4863 { 1233, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1233 = J4_cmpgt_tp0_jump_nt
4864 { 1234, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1234 = J4_cmpgt_tp0_jump_t
4865 { 1235, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1235 = J4_cmpgt_tp1_jump_nt
4866 { 1236, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1236 = J4_cmpgt_tp1_jump_t
4867 { 1237, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c28ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1237 = J4_cmpgti_f_jumpnv_nt
4868 { 1238, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804c28ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1238 = J4_cmpgti_f_jumpnv_t
4869 { 1239, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1239 = J4_cmpgti_fp0_jump_nt
4870 { 1240, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1240 = J4_cmpgti_fp0_jump_t
4871 { 1241, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1241 = J4_cmpgti_fp1_jump_nt
4872 { 1242, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1242 = J4_cmpgti_fp1_jump_t
4873 { 1243, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804428ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1243 = J4_cmpgti_t_jumpnv_nt
4874 { 1244, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804428ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1244 = J4_cmpgti_t_jumpnv_t
4875 { 1245, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1245 = J4_cmpgti_tp0_jump_nt
4876 { 1246, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1246 = J4_cmpgti_tp0_jump_t
4877 { 1247, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1247 = J4_cmpgti_tp1_jump_nt
4878 { 1248, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1248 = J4_cmpgti_tp1_jump_t
4879 { 1249, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c28ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1249 = J4_cmpgtn1_f_jumpnv_nt
4880 { 1250, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804c28ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1250 = J4_cmpgtn1_f_jumpnv_t
4881 { 1251, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1251 = J4_cmpgtn1_fp0_jump_nt
4882 { 1252, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1252 = J4_cmpgtn1_fp0_jump_t
4883 { 1253, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1253 = J4_cmpgtn1_fp1_jump_nt
4884 { 1254, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1254 = J4_cmpgtn1_fp1_jump_t
4885 { 1255, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804428ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1255 = J4_cmpgtn1_t_jumpnv_nt
4886 { 1256, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804428ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1256 = J4_cmpgtn1_t_jumpnv_t
4887 { 1257, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1257 = J4_cmpgtn1_tp0_jump_nt
4888 { 1258, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1258 = J4_cmpgtn1_tp0_jump_t
4889 { 1259, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1259 = J4_cmpgtn1_tp1_jump_nt
4890 { 1260, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1260 = J4_cmpgtn1_tp1_jump_t
4891 { 1261, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c28ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1261 = J4_cmpgtu_f_jumpnv_nt
4892 { 1262, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804c28ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1262 = J4_cmpgtu_f_jumpnv_t
4893 { 1263, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1263 = J4_cmpgtu_fp0_jump_nt
4894 { 1264, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1264 = J4_cmpgtu_fp0_jump_t
4895 { 1265, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1265 = J4_cmpgtu_fp1_jump_nt
4896 { 1266, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1266 = J4_cmpgtu_fp1_jump_t
4897 { 1267, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804428ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1267 = J4_cmpgtu_t_jumpnv_nt
4898 { 1268, 3, 0, 4, 117, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804428ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1268 = J4_cmpgtu_t_jumpnv_t
4899 { 1269, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1269 = J4_cmpgtu_tp0_jump_nt
4900 { 1270, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1270 = J4_cmpgtu_tp0_jump_t
4901 { 1271, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1271 = J4_cmpgtu_tp1_jump_nt
4902 { 1272, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList32, ImplicitList33, OperandInfo168, -1 ,nullptr }, // Inst #1272 = J4_cmpgtu_tp1_jump_t
4903 { 1273, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c28ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1273 = J4_cmpgtui_f_jumpnv_nt
4904 { 1274, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804c28ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1274 = J4_cmpgtui_f_jumpnv_t
4905 { 1275, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1275 = J4_cmpgtui_fp0_jump_nt
4906 { 1276, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1276 = J4_cmpgtui_fp0_jump_t
4907 { 1277, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1277 = J4_cmpgtui_fp1_jump_nt
4908 { 1278, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1278 = J4_cmpgtui_fp1_jump_t
4909 { 1279, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804428ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1279 = J4_cmpgtui_t_jumpnv_nt
4910 { 1280, 3, 0, 4, 119, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974804428ULL, nullptr, ImplicitList19, OperandInfo169, -1 ,nullptr }, // Inst #1280 = J4_cmpgtui_t_jumpnv_t
4911 { 1281, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1281 = J4_cmpgtui_tp0_jump_nt
4912 { 1282, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1282 = J4_cmpgtui_tp0_jump_t
4913 { 1283, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1283 = J4_cmpgtui_tp1_jump_nt
4914 { 1284, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList32, ImplicitList33, OperandInfo170, -1 ,nullptr }, // Inst #1284 = J4_cmpgtui_tp1_jump_t
4915 { 1285, 3, 0, 4, 121, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814c28ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1285 = J4_cmplt_f_jumpnv_nt
4916 { 1286, 3, 0, 4, 121, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974814c28ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1286 = J4_cmplt_f_jumpnv_t
4917 { 1287, 3, 0, 4, 121, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814428ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1287 = J4_cmplt_t_jumpnv_nt
4918 { 1288, 3, 0, 4, 121, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974814428ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1288 = J4_cmplt_t_jumpnv_t
4919 { 1289, 3, 0, 4, 121, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814c28ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1289 = J4_cmpltu_f_jumpnv_nt
4920 { 1290, 3, 0, 4, 121, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974814c28ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1290 = J4_cmpltu_f_jumpnv_t
4921 { 1291, 3, 0, 4, 121, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814428ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1291 = J4_cmpltu_t_jumpnv_nt
4922 { 1292, 3, 0, 4, 121, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009974814428ULL, nullptr, ImplicitList19, OperandInfo55, -1 ,nullptr }, // Inst #1292 = J4_cmpltu_t_jumpnv_t
4923 { 1293, 1, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #1293 = J4_hintjumpr
4924 { 1294, 3, 1, 4, 122, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5974808004ULL, nullptr, ImplicitList19, OperandInfo170, -1 ,nullptr }, // Inst #1294 = J4_jumpseti
4925 { 1295, 3, 1, 4, 122, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5974808004ULL, nullptr, ImplicitList19, OperandInfo168, -1 ,nullptr }, // Inst #1295 = J4_jumpsetr
4926 { 1296, 2, 0, 4, 123, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9972804c28ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1296 = J4_tstbit0_f_jumpnv_nt
4927 { 1297, 2, 0, 4, 123, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009972804c28ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1297 = J4_tstbit0_f_jumpnv_t
4928 { 1298, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801c04ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1298 = J4_tstbit0_fp0_jump_nt
4929 { 1299, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007972801c04ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1299 = J4_tstbit0_fp0_jump_t
4930 { 1300, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801c04ULL, ImplicitList32, ImplicitList33, OperandInfo171, -1 ,nullptr }, // Inst #1300 = J4_tstbit0_fp1_jump_nt
4931 { 1301, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007972801c04ULL, ImplicitList32, ImplicitList33, OperandInfo171, -1 ,nullptr }, // Inst #1301 = J4_tstbit0_fp1_jump_t
4932 { 1302, 2, 0, 4, 123, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9972804428ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1302 = J4_tstbit0_t_jumpnv_nt
4933 { 1303, 2, 0, 4, 123, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2009972804428ULL, nullptr, ImplicitList19, OperandInfo37, -1 ,nullptr }, // Inst #1303 = J4_tstbit0_t_jumpnv_t
4934 { 1304, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801404ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1304 = J4_tstbit0_tp0_jump_nt
4935 { 1305, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007972801404ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1305 = J4_tstbit0_tp0_jump_t
4936 { 1306, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801404ULL, ImplicitList32, ImplicitList33, OperandInfo171, -1 ,nullptr }, // Inst #1306 = J4_tstbit0_tp1_jump_nt
4937 { 1307, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007972801404ULL, ImplicitList32, ImplicitList33, OperandInfo171, -1 ,nullptr }, // Inst #1307 = J4_tstbit0_tp1_jump_t
5166 { 1536, 2, 1, 4, 28, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x2809000000025ULL, ImplicitList34, ImplicitList36, OperandInfo51, -1 ,nullptr }, // Inst #1536 = L4_return
5167 { 1537, 3, 1, 4, 23, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000000c25ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1537 = L4_return_f
5168 { 1538, 3, 1, 4, 24, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000001c25ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1538 = L4_return_fnew_pnt
5169 { 1539, 3, 1, 4, 24, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000001c25ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1539 = L4_return_fnew_pt
5170 { 1540, 3, 1, 4, 23, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000000425ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1540 = L4_return_t
5171 { 1541, 3, 1, 4, 24, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000001425ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1541 = L4_return_tnew_pnt
5172 { 1542, 3, 1, 4, 24, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000001425ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1542 = L4_return_tnew_pt
5500 { 1870, 1, 0, 4, 38, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, ImplicitList19, OperandInfo71, -1 ,nullptr }, // Inst #1870 = PS_jmpret
5501 { 1871, 2, 0, 4, 16, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1871 = PS_jmpretf
5502 { 1872, 2, 0, 4, 108, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000001c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1872 = PS_jmpretfnew
5503 { 1873, 2, 0, 4, 108, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x2001000001c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1873 = PS_jmpretfnewpt
5504 { 1874, 2, 0, 4, 16, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1874 = PS_jmprett
5505 { 1875, 2, 0, 4, 108, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000001424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1875 = PS_jmprettnew
5506 { 1876, 2, 0, 4, 108, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x2001000001424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1876 = PS_jmprettnewpt
5525 { 1895, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb10800024ULL, nullptr, ImplicitList38, OperandInfo2, -1 ,nullptr }, // Inst #1895 = RESTORE_DEALLOC_RET_JMP_V4
5526 { 1896, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb11800024ULL, nullptr, ImplicitList38, OperandInfo2, -1 ,nullptr }, // Inst #1896 = RESTORE_DEALLOC_RET_JMP_V4_EXT
5527 { 1897, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb11800024ULL, nullptr, ImplicitList39, OperandInfo2, -1 ,nullptr }, // Inst #1897 = RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
5528 { 1898, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb10800024ULL, nullptr, ImplicitList39, OperandInfo2, -1 ,nullptr }, // Inst #1898 = RESTORE_DEALLOC_RET_JMP_V4_PIC
6014 { 2384, 0, 0, 4, 178, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000002bULL, ImplicitList46, ImplicitList19, nullptr, -1 ,nullptr }, // Inst #2384 = SL2_jumpr31
6015 { 2385, 0, 0, 4, 178, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000c2bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr }, // Inst #2385 = SL2_jumpr31_f
6016 { 2386, 0, 0, 4, 178, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001c2bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr }, // Inst #2386 = SL2_jumpr31_fnew
6017 { 2387, 0, 0, 4, 178, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000042bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr }, // Inst #2387 = SL2_jumpr31_t
6018 { 2388, 0, 0, 4, 178, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000142bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr }, // Inst #2388 = SL2_jumpr31_tnew
6024 { 2394, 0, 0, 4, 179, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x80900000002bULL, ImplicitList44, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #2394 = SL2_return
6025 { 2395, 0, 0, 4, 179, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000000c2bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #2395 = SL2_return_f
6026 { 2396, 0, 0, 4, 179, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000001c2bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #2396 = SL2_return_fnew
6027 { 2397, 0, 0, 4, 179, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x80900000042bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #2397 = SL2_return_t
6028 { 2398, 0, 0, 4, 179, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x80900000142bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #2398 = SL2_return_tnew
gen/lib/Target/Lanai/LanaiGenInstrInfo.inc 372 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
396 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
399 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
455 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
456 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
521 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
522 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
567 { 197, 2, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #197 = BRCC
568 { 198, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #198 = BRIND_CC
569 { 199, 3, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #199 = BRIND_CCA
570 { 200, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #200 = BRR
571 { 201, 1, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #201 = BT
572 { 202, 1, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #202 = JR
600 { 230, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #230 = RET
gen/lib/Target/MSP430/MSP430GenInstrInfo.inc 643 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
667 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
670 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
726 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
727 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
792 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
793 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
962 { 321, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #321 = Bi
963 { 322, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #322 = Bm
964 { 323, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #323 = Br
1018 { 377, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #377 = JCC
1019 { 378, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #378 = JMP
1049 { 408, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #408 = RET
1050 { 409, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #409 = RETI
gen/lib/Target/Mips/MipsGenInstrInfo.inc 4817 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
4841 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
4844 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
4900 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
4901 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
4966 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
4967 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
5059 { 244, 1, 0, 4, 369, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr }, // Inst #244 = B
5060 { 245, 1, 0, 4, 911, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #245 = BAL_BR
5061 { 246, 1, 0, 4, 938, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #246 = BAL_BR_MM
5102 { 287, 1, 0, 4, 937, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr }, // Inst #287 = B_MM
5107 { 292, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #292 = BteqzT8CmpX16
5108 { 293, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #293 = BteqzT8CmpiX16
5109 { 294, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #294 = BteqzT8SltX16
5110 { 295, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #295 = BteqzT8SltiX16
5111 { 296, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #296 = BteqzT8SltiuX16
5112 { 297, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #297 = BteqzT8SltuX16
5113 { 298, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #298 = BtnezT8CmpX16
5114 { 299, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #299 = BtnezT8CmpiX16
5115 { 300, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #300 = BtnezT8SltX16
5116 { 301, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #301 = BtnezT8SltiX16
5117 { 302, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #302 = BtnezT8SltiuX16
5118 { 303, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #303 = BtnezT8SltuX16
5143 { 328, 0, 0, 4, 916, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #328 = ERet
5208 { 393, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #393 = MIPSeh_return32
5209 { 394, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #394 = MIPSeh_return64
5255 { 440, 1, 0, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #440 = PseudoIndirectBranch
5256 { 441, 1, 0, 4, 1012, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #441 = PseudoIndirectBranch64
5257 { 442, 1, 0, 4, 1016, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #442 = PseudoIndirectBranch64R6
5258 { 443, 1, 0, 4, 928, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #443 = PseudoIndirectBranchR6
5259 { 444, 1, 0, 4, 957, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #444 = PseudoIndirectBranch_MM
5260 { 445, 1, 0, 4, 990, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #445 = PseudoIndirectBranch_MMR6
5261 { 446, 1, 0, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #446 = PseudoIndirectHazardBranch
5262 { 447, 1, 0, 4, 1012, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #447 = PseudoIndirectHazardBranch64
5263 { 448, 1, 0, 4, 1016, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #448 = PseudoIndrectHazardBranch64R6
5264 { 449, 1, 0, 4, 928, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #449 = PseudoIndrectHazardBranchR6
5289 { 474, 1, 0, 4, 383, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #474 = PseudoReturn
5290 { 475, 1, 0, 4, 1008, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #475 = PseudoReturn64
5315 { 500, 0, 0, 4, 377, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #500 = RetRA
5316 { 501, 0, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #501 = RetRA16
5373 { 558, 1, 0, 4, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #558 = TAILCALL
5374 { 559, 1, 0, 4, 1015, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #559 = TAILCALL64R6REG
5375 { 560, 1, 0, 4, 1015, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #560 = TAILCALLHB64R6REG
5376 { 561, 1, 0, 4, 929, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #561 = TAILCALLHBR6REG
5377 { 562, 1, 0, 4, 929, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #562 = TAILCALLR6REG
5378 { 563, 1, 0, 4, 380, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #563 = TAILCALLREG
5379 { 564, 1, 0, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #564 = TAILCALLREG64
5380 { 565, 1, 0, 4, 380, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #565 = TAILCALLREGHB
5381 { 566, 1, 0, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #566 = TAILCALLREGHB64
5382 { 567, 1, 0, 4, 955, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #567 = TAILCALLREG_MM
5383 { 568, 1, 0, 4, 997, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #568 = TAILCALLREG_MMR6
5384 { 569, 1, 0, 4, 956, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #569 = TAILCALL_MM
5385 { 570, 1, 0, 4, 998, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #570 = TAILCALL_MMR6
5386 { 571, 0, 0, 4, 397, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #571 = TRAP
5387 { 572, 0, 0, 4, 973, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #572 = TRAP_MM
5538 { 723, 1, 0, 2, 937, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr }, // Inst #723 = B16_MM
5540 { 725, 1, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #725 = BAL
5541 { 726, 1, 0, 4, 918, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #726 = BALC
5542 { 727, 1, 0, 4, 991, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #727 = BALC_MMR6
5545 { 730, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo175, -1 ,nullptr }, // Inst #730 = BBIT0
5546 { 731, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo175, -1 ,nullptr }, // Inst #731 = BBIT032
5547 { 732, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo175, -1 ,nullptr }, // Inst #732 = BBIT1
5548 { 733, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo175, -1 ,nullptr }, // Inst #733 = BBIT132
5549 { 734, 1, 0, 4, 921, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #734 = BC
5550 { 735, 1, 0, 2, 974, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr }, // Inst #735 = BC16_MMR6
5551 { 736, 2, 0, 4, 1219, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #736 = BC1EQZ
5552 { 737, 2, 0, 4, 975, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo176, -1 ,nullptr }, // Inst #737 = BC1EQZC_MMR6
5553 { 738, 2, 0, 4, 682, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #738 = BC1F
5554 { 739, 2, 0, 4, 683, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #739 = BC1FL
5555 { 740, 2, 0, 4, 939, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #740 = BC1F_MM
5556 { 741, 2, 0, 4, 1219, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #741 = BC1NEZ
5557 { 742, 2, 0, 4, 975, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo176, -1 ,nullptr }, // Inst #742 = BC1NEZC_MMR6
5558 { 743, 2, 0, 4, 684, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #743 = BC1T
5559 { 744, 2, 0, 4, 685, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #744 = BC1TL
5560 { 745, 2, 0, 4, 940, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #745 = BC1T_MM
5561 { 746, 2, 0, 4, 922, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #746 = BC2EQZ
5562 { 747, 2, 0, 4, 976, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo178, -1 ,nullptr }, // Inst #747 = BC2EQZC_MMR6
5563 { 748, 2, 0, 4, 922, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #748 = BC2NEZ
5564 { 749, 2, 0, 4, 976, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo178, -1 ,nullptr }, // Inst #749 = BC2NEZC_MMR6
5573 { 758, 1, 0, 4, 974, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #758 = BC_MMR6
5574 { 759, 3, 0, 4, 912, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #759 = BEQ
5575 { 760, 3, 0, 4, 1001, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #760 = BEQ64
5576 { 761, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #761 = BEQC
5577 { 762, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #762 = BEQC64
5578 { 763, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #763 = BEQC_MMR6
5579 { 764, 3, 0, 4, 372, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #764 = BEQL
5580 { 765, 2, 0, 2, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #765 = BEQZ16_MM
5581 { 766, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #766 = BEQZALC
5582 { 767, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #767 = BEQZALC_MMR6
5583 { 768, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #768 = BEQZC
5584 { 769, 2, 0, 2, 978, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #769 = BEQZC16_MMR6
5585 { 770, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo98, -1 ,nullptr }, // Inst #770 = BEQZC64
5586 { 771, 2, 0, 4, 942, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #771 = BEQZC_MM
5587 { 772, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #772 = BEQZC_MMR6
5588 { 773, 3, 0, 4, 943, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #773 = BEQ_MM
5589 { 774, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #774 = BGEC
5590 { 775, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #775 = BGEC64
5591 { 776, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #776 = BGEC_MMR6
5592 { 777, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #777 = BGEUC
5593 { 778, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #778 = BGEUC64
5594 { 779, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #779 = BGEUC_MMR6
5595 { 780, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #780 = BGEZ
5596 { 781, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo98, -1 ,nullptr }, // Inst #781 = BGEZ64
5598 { 783, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #783 = BGEZALC
5599 { 784, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #784 = BGEZALC_MMR6
5603 { 788, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #788 = BGEZC
5604 { 789, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo98, -1 ,nullptr }, // Inst #789 = BGEZC64
5605 { 790, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #790 = BGEZC_MMR6
5606 { 791, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #791 = BGEZL
5607 { 792, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #792 = BGEZ_MM
5608 { 793, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #793 = BGTZ
5609 { 794, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo98, -1 ,nullptr }, // Inst #794 = BGTZ64
5610 { 795, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #795 = BGTZALC
5611 { 796, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #796 = BGTZALC_MMR6
5612 { 797, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #797 = BGTZC
5613 { 798, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo98, -1 ,nullptr }, // Inst #798 = BGTZC64
5614 { 799, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #799 = BGTZC_MMR6
5615 { 800, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #800 = BGTZL
5616 { 801, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #801 = BGTZ_MM
5637 { 822, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #822 = BLEZ
5638 { 823, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo98, -1 ,nullptr }, // Inst #823 = BLEZ64
5639 { 824, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #824 = BLEZALC
5640 { 825, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #825 = BLEZALC_MMR6
5641 { 826, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #826 = BLEZC
5642 { 827, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo98, -1 ,nullptr }, // Inst #827 = BLEZC64
5643 { 828, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #828 = BLEZC_MMR6
5644 { 829, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #829 = BLEZL
5645 { 830, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #830 = BLEZ_MM
5646 { 831, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #831 = BLTC
5647 { 832, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #832 = BLTC64
5648 { 833, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #833 = BLTC_MMR6
5649 { 834, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #834 = BLTUC
5650 { 835, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #835 = BLTUC64
5651 { 836, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #836 = BLTUC_MMR6
5652 { 837, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #837 = BLTZ
5653 { 838, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo98, -1 ,nullptr }, // Inst #838 = BLTZ64
5655 { 840, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #840 = BLTZALC
5656 { 841, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #841 = BLTZALC_MMR6
5660 { 845, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #845 = BLTZC
5661 { 846, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo98, -1 ,nullptr }, // Inst #846 = BLTZC64
5662 { 847, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #847 = BLTZC_MMR6
5663 { 848, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #848 = BLTZL
5664 { 849, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #849 = BLTZ_MM
5669 { 854, 3, 0, 4, 912, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #854 = BNE
5670 { 855, 3, 0, 4, 1001, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #855 = BNE64
5671 { 856, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #856 = BNEC
5672 { 857, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #857 = BNEC64
5673 { 858, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #858 = BNEC_MMR6
5682 { 867, 3, 0, 4, 372, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #867 = BNEL
5683 { 868, 2, 0, 2, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #868 = BNEZ16_MM
5684 { 869, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #869 = BNEZALC
5685 { 870, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #870 = BNEZALC_MMR6
5686 { 871, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #871 = BNEZC
5687 { 872, 2, 0, 2, 978, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #872 = BNEZC16_MMR6
5688 { 873, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo98, -1 ,nullptr }, // Inst #873 = BNEZC64
5689 { 874, 2, 0, 4, 942, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #874 = BNEZC_MM
5690 { 875, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #875 = BNEZC_MMR6
5691 { 876, 3, 0, 4, 943, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #876 = BNE_MM
5692 { 877, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #877 = BNVC
5693 { 878, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #878 = BNVC_MMR6
5694 { 879, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo185, -1 ,nullptr }, // Inst #879 = BNZ_B
5695 { 880, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo186, -1 ,nullptr }, // Inst #880 = BNZ_D
5696 { 881, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo187, -1 ,nullptr }, // Inst #881 = BNZ_H
5697 { 882, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo185, -1 ,nullptr }, // Inst #882 = BNZ_V
5698 { 883, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo188, -1 ,nullptr }, // Inst #883 = BNZ_W
5699 { 884, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #884 = BOVC
5700 { 885, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #885 = BOVC_MMR6
5701 { 886, 1, 0, 4, 1355, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #886 = BPOSGE32
5702 { 887, 1, 0, 4, 1658, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #887 = BPOSGE32C_MMR3
5703 { 888, 1, 0, 4, 1506, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #888 = BPOSGE32_MM
5719 { 904, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo185, -1 ,nullptr }, // Inst #904 = BZ_B
5720 { 905, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo186, -1 ,nullptr }, // Inst #905 = BZ_D
5721 { 906, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo187, -1 ,nullptr }, // Inst #906 = BZ_H
5722 { 907, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo185, -1 ,nullptr }, // Inst #907 = BZ_V
5723 { 908, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo188, -1 ,nullptr }, // Inst #908 = BZ_W
5724 { 909, 2, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #909 = BeqzRxImm16
5725 { 910, 2, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #910 = BeqzRxImmX16
5726 { 911, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #911 = Bimm16
5727 { 912, 1, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #912 = BimmX16
5728 { 913, 2, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #913 = BnezRxImm16
5729 { 914, 2, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #914 = BnezRxImmX16
5731 { 916, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #916 = Bteqz16
5732 { 917, 1, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #917 = BteqzX16
5733 { 918, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #918 = Btnez16
5734 { 919, 1, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #919 = BtnezX16
6459 { 1644, 1, 0, 4, 914, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1644 = J
6478 { 1663, 2, 0, 4, 996, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo103, -1 ,nullptr }, // Inst #1663 = JIALC_MMR6
6479 { 1664, 2, 0, 4, 925, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo103, -1 ,nullptr }, // Inst #1664 = JIC
6480 { 1665, 2, 0, 4, 1011, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo101, -1 ,nullptr }, // Inst #1665 = JIC64
6481 { 1666, 2, 0, 4, 984, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo103, -1 ,nullptr }, // Inst #1666 = JIC_MMR6
6482 { 1667, 1, 0, 4, 915, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1667 = JR
6484 { 1669, 1, 0, 4, 1003, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1669 = JR64
6485 { 1670, 1, 0, 2, 985, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1670 = JRADDIUSP
6486 { 1671, 1, 0, 2, 986, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1671 = JRC16_MM
6488 { 1673, 1, 0, 2, 985, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1673 = JRCADDIUSP_MMR6
6489 { 1674, 1, 0, 4, 381, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1674 = JR_HB
6490 { 1675, 1, 0, 4, 1006, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1675 = JR_HB64
6491 { 1676, 1, 0, 4, 1014, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1676 = JR_HB64_R6
6492 { 1677, 1, 0, 4, 926, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1677 = JR_HB_R6
6493 { 1678, 1, 0, 4, 946, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1678 = JR_MM
6494 { 1679, 1, 0, 4, 947, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1679 = J_MM
6496 { 1681, 1, 0, 6, 933, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1681 = JalB16
6497 { 1682, 0, 0, 2, 931, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1682 = JrRa16
6498 { 1683, 0, 0, 2, 931, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1683 = JrcRa16
6499 { 1684, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #1684 = JrcRx16
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 6633 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
6657 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
6660 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
6716 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
6717 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
6782 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
6783 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
6859 { 228, 2, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #228 = CBranch
6860 { 229, 2, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #229 = CBranchOther
7178 { 547, 1, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #547 = GOTO
8327 { 1696, 0, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1696 = Return
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 2910 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
2934 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
2937 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
2993 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
2994 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
3059 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
3060 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
3275 { 367, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #367 = B
3276 { 368, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #368 = BA
3277 { 369, 2, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #369 = BC
3278 { 370, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #370 = BCC
3279 { 371, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #371 = BCCA
3280 { 372, 2, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #372 = BCCCTR
3281 { 373, 2, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #373 = BCCCTR8
3286 { 378, 2, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList15, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #378 = BCCLR
3288 { 380, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #380 = BCCTR
3289 { 381, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #381 = BCCTR8
3290 { 382, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #382 = BCCTR8n
3295 { 387, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #387 = BCCTRn
3310 { 402, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList15, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #402 = BCLR
3313 { 405, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #405 = BCLRn
3316 { 408, 0, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, nullptr, nullptr, -1 ,nullptr }, // Inst #408 = BCTR
3317 { 409, 0, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, nullptr, nullptr, -1 ,nullptr }, // Inst #409 = BCTR8
3321 { 413, 2, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #413 = BCn
3322 { 414, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #414 = BDNZ
3323 { 415, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, ImplicitList10, OperandInfo2, -1 ,nullptr }, // Inst #415 = BDNZ8
3324 { 416, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #416 = BDNZA
3325 { 417, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #417 = BDNZAm
3326 { 418, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #418 = BDNZAp
3331 { 423, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #423 = BDNZLR
3332 { 424, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList19, ImplicitList10, nullptr, -1 ,nullptr }, // Inst #424 = BDNZLR8
3336 { 428, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #428 = BDNZLRm
3337 { 429, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #429 = BDNZLRp
3340 { 432, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #432 = BDNZm
3341 { 433, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #433 = BDNZp
3342 { 434, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #434 = BDZ
3343 { 435, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, ImplicitList10, OperandInfo2, -1 ,nullptr }, // Inst #435 = BDZ8
3344 { 436, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #436 = BDZA
3345 { 437, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #437 = BDZAm
3346 { 438, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #438 = BDZAp
3351 { 443, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #443 = BDZLR
3352 { 444, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList19, ImplicitList10, nullptr, -1 ,nullptr }, // Inst #444 = BDZLR8
3356 { 448, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #448 = BDZLRm
3357 { 449, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #449 = BDZLRp
3360 { 452, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #452 = BDZm
3361 { 453, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #453 = BDZp
3371 { 463, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList15, nullptr, nullptr, -1 ,nullptr }, // Inst #463 = BLR
3372 { 464, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList20, nullptr, nullptr, -1 ,nullptr }, // Inst #464 = BLR8
3522 { 614, 1, 0, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #614 = EH_SjLj_LongJmp32
3523 { 615, 1, 0, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #615 = EH_SjLj_LongJmp64
3526 { 618, 1, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #618 = EH_SjLj_Setup
4527 { 1619, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #1619 = TAILB
4528 { 1620, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #1620 = TAILB8
4529 { 1621, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1621 = TAILBA
4530 { 1622, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1622 = TAILBA8
4531 { 1623, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, nullptr, nullptr, -1 ,nullptr }, // Inst #1623 = TAILBCTR
4532 { 1624, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, nullptr, -1 ,nullptr }, // Inst #1624 = TAILBCTR8
4537 { 1629, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1629 = TCRETURNai
4538 { 1630, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1630 = TCRETURNai8
4539 { 1631, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1631 = TCRETURNdi
4540 { 1632, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1632 = TCRETURNdi8
4541 { 1633, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #1633 = TCRETURNri
4542 { 1634, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1634 = TCRETURNri8
4560 { 1652, 0, 0, 4, 299, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1652 = TRAP
gen/lib/Target/RISCV/RISCVGenInstrInfo.inc 664 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
688 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
691 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
747 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
748 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
813 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
814 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
842 { 180, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #180 = PseudoBR
843 { 181, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList2, OperandInfo40, -1 ,nullptr }, // Inst #181 = PseudoBRIND
874 { 212, 0, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #212 = PseudoRET
879 { 217, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #217 = PseudoTAIL
880 { 218, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #218 = PseudoTAILIndirect
965 { 303, 3, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #303 = BEQ
966 { 304, 3, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #304 = BGE
967 { 305, 3, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #305 = BGEU
968 { 306, 3, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #306 = BLT
969 { 307, 3, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #307 = BLTU
970 { 308, 3, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #308 = BNE
989 { 327, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0xfULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #327 = C_BEQZ
990 { 328, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0xfULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #328 = C_BNEZ
1000 { 338, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #338 = C_J
1003 { 341, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #341 = C_JR
1121 { 459, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #459 = MRET
1157 { 495, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #495 = SRET
1166 { 504, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #504 = URET
gen/lib/Target/Sparc/SparcGenInstrInfo.inc 932 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
956 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
959 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
1015 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
1016 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
1081 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
1082 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
1144 { 214, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #214 = BA
1145 { 215, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList4, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #215 = BCOND
1146 { 216, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #216 = BCONDA
1147 { 217, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #217 = BINDri
1148 { 218, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #218 = BINDrr
1150 { 220, 3, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #220 = BPFCC
1151 { 221, 3, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #221 = BPFCCA
1152 { 222, 3, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #222 = BPFCCANT
1153 { 223, 3, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #223 = BPFCCNT
1154 { 224, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #224 = BPGEZapn
1155 { 225, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #225 = BPGEZapt
1156 { 226, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #226 = BPGEZnapn
1157 { 227, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #227 = BPGEZnapt
1158 { 228, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #228 = BPGZapn
1159 { 229, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #229 = BPGZapt
1160 { 230, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #230 = BPGZnapn
1161 { 231, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #231 = BPGZnapt
1162 { 232, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #232 = BPICC
1163 { 233, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #233 = BPICCA
1164 { 234, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #234 = BPICCANT
1165 { 235, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #235 = BPICCNT
1166 { 236, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #236 = BPLEZapn
1167 { 237, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #237 = BPLEZapt
1168 { 238, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #238 = BPLEZnapn
1169 { 239, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #239 = BPLEZnapt
1170 { 240, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #240 = BPLZapn
1171 { 241, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #241 = BPLZapt
1172 { 242, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #242 = BPLZnapn
1173 { 243, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #243 = BPLZnapt
1174 { 244, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #244 = BPNZapn
1175 { 245, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #245 = BPNZapt
1176 { 246, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #246 = BPNZnapn
1177 { 247, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #247 = BPNZnapt
1178 { 248, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList4, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #248 = BPXCC
1179 { 249, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #249 = BPXCCA
1180 { 250, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #250 = BPXCCANT
1181 { 251, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #251 = BPXCCNT
1182 { 252, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #252 = BPZapn
1183 { 253, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #253 = BPZapt
1184 { 254, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #254 = BPZnapn
1185 { 255, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #255 = BPZnapt
1194 { 264, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #264 = CBCOND
1195 { 265, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #265 = CBCONDA
1226 { 296, 2, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #296 = FBCOND
1227 { 297, 2, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #297 = FBCONDA
1378 { 448, 3, 1, 4, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #448 = JMPLri
1379 { 449, 3, 1, 4, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #449 = JMPLrr
1479 { 549, 1, 0, 4, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #549 = RET
1480 { 550, 1, 0, 4, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #550 = RETL
1481 { 551, 2, 0, 4, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #551 = RETTri
1482 { 552, 2, 0, 4, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #552 = RETTrr
1566 { 636, 0, 0, 4, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #636 = TA5
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 4322 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
4346 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
4349 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
4405 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
4406 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
4471 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
4472 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
4579 { 259, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #259 = CGIBCall
4580 { 260, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #260 = CGIBReturn
4581 { 261, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #261 = CGRBCall
4582 { 262, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #262 = CGRBReturn
4584 { 264, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #264 = CIBCall
4585 { 265, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #265 = CIBReturn
4589 { 269, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #269 = CLGIBCall
4590 { 270, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #270 = CLGIBReturn
4591 { 271, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #271 = CLGRBCall
4592 { 272, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #272 = CLGRBReturn
4593 { 273, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #273 = CLIBCall
4594 { 274, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #274 = CLIBReturn
4596 { 276, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #276 = CLRBCall
4597 { 277, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #277 = CLRBReturn
4600 { 280, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #280 = CRBCall
4601 { 281, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #281 = CRBReturn
4603 { 283, 2, 0, 2, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList2, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #283 = CallBCR
4604 { 284, 0, 0, 2, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #284 = CallBR
4606 { 286, 3, 0, 6, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x40000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #286 = CallBRCL
4607 { 287, 1, 0, 6, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #287 = CallJG
4608 { 288, 2, 0, 2, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #288 = CondReturn
4692 { 372, 0, 0, 2, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #372 = Return
4804 { 484, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #484 = B
4811 { 491, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #491 = BAsmE
4812 { 492, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #492 = BAsmH
4813 { 493, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #493 = BAsmHE
4814 { 494, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #494 = BAsmL
4815 { 495, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #495 = BAsmLE
4816 { 496, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #496 = BAsmLH
4817 { 497, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #497 = BAsmM
4818 { 498, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #498 = BAsmNE
4819 { 499, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #499 = BAsmNH
4820 { 500, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #500 = BAsmNHE
4821 { 501, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #501 = BAsmNL
4822 { 502, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #502 = BAsmNLE
4823 { 503, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #503 = BAsmNLH
4824 { 504, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #504 = BAsmNM
4825 { 505, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #505 = BAsmNO
4826 { 506, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #506 = BAsmNP
4827 { 507, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #507 = BAsmNZ
4828 { 508, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #508 = BAsmO
4829 { 509, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #509 = BAsmP
4830 { 510, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #510 = BAsmZ
4831 { 511, 5, 0, 4, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x40008ULL, ImplicitList1, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #511 = BC
4832 { 512, 4, 0, 4, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #512 = BCAsm
4833 { 513, 3, 0, 2, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #513 = BCR
4834 { 514, 2, 0, 2, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #514 = BCRAsm
4835 { 515, 5, 1, 4, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #515 = BCT
4836 { 516, 5, 1, 6, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0xcULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #516 = BCTG
4837 { 517, 3, 1, 4, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #517 = BCTGR
4838 { 518, 3, 1, 2, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #518 = BCTR
4839 { 519, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #519 = BI
4840 { 520, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #520 = BIAsmE
4841 { 521, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #521 = BIAsmH
4842 { 522, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #522 = BIAsmHE
4843 { 523, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #523 = BIAsmL
4844 { 524, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #524 = BIAsmLE
4845 { 525, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #525 = BIAsmLH
4846 { 526, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #526 = BIAsmM
4847 { 527, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #527 = BIAsmNE
4848 { 528, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #528 = BIAsmNH
4849 { 529, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #529 = BIAsmNHE
4850 { 530, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #530 = BIAsmNL
4851 { 531, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #531 = BIAsmNLE
4852 { 532, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #532 = BIAsmNLH
4853 { 533, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #533 = BIAsmNM
4854 { 534, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #534 = BIAsmNO
4855 { 535, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #535 = BIAsmNP
4856 { 536, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #536 = BIAsmNZ
4857 { 537, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #537 = BIAsmO
4858 { 538, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #538 = BIAsmP
4859 { 539, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #539 = BIAsmZ
4860 { 540, 5, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x4000cULL, ImplicitList1, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #540 = BIC
4861 { 541, 4, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #541 = BICAsm
4864 { 544, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #544 = BR
4867 { 547, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #547 = BRAsmE
4868 { 548, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #548 = BRAsmH
4869 { 549, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #549 = BRAsmHE
4870 { 550, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #550 = BRAsmL
4871 { 551, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #551 = BRAsmLE
4872 { 552, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #552 = BRAsmLH
4873 { 553, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #553 = BRAsmM
4874 { 554, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #554 = BRAsmNE
4875 { 555, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #555 = BRAsmNH
4876 { 556, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #556 = BRAsmNHE
4877 { 557, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #557 = BRAsmNL
4878 { 558, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #558 = BRAsmNLE
4879 { 559, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #559 = BRAsmNLH
4880 { 560, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #560 = BRAsmNM
4881 { 561, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #561 = BRAsmNO
4882 { 562, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #562 = BRAsmNP
4883 { 563, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #563 = BRAsmNZ
4884 { 564, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #564 = BRAsmO
4885 { 565, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #565 = BRAsmP
4886 { 566, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #566 = BRAsmZ
4887 { 567, 3, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #567 = BRC
4888 { 568, 2, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #568 = BRCAsm
4889 { 569, 3, 0, 6, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #569 = BRCL
4890 { 570, 2, 0, 6, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #570 = BRCLAsm
4891 { 571, 3, 1, 4, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #571 = BRCT
4892 { 572, 3, 1, 4, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #572 = BRCTG
4893 { 573, 3, 1, 6, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #573 = BRCTH
4894 { 574, 4, 1, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo130, -1 ,nullptr }, // Inst #574 = BRXH
4895 { 575, 4, 1, 6, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo131, -1 ,nullptr }, // Inst #575 = BRXHG
4896 { 576, 4, 1, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo130, -1 ,nullptr }, // Inst #576 = BRXLE
4897 { 577, 4, 1, 6, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo131, -1 ,nullptr }, // Inst #577 = BRXLG
4900 { 580, 2, 0, 2, 320, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #580 = BSM
4901 { 581, 5, 1, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #581 = BXH
4902 { 582, 5, 1, 6, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #582 = BXHG
4903 { 583, 5, 1, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #583 = BXLE
4904 { 584, 5, 1, 6, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #584 = BXLEG
4975 { 655, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #655 = CGIB
4976 { 656, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #656 = CGIBAsm
4977 { 657, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #657 = CGIBAsmE
4978 { 658, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #658 = CGIBAsmH
4979 { 659, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #659 = CGIBAsmHE
4980 { 660, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #660 = CGIBAsmL
4981 { 661, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #661 = CGIBAsmLE
4982 { 662, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #662 = CGIBAsmLH
4983 { 663, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #663 = CGIBAsmNE
4984 { 664, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #664 = CGIBAsmNH
4985 { 665, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #665 = CGIBAsmNHE
4986 { 666, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #666 = CGIBAsmNL
4987 { 667, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #667 = CGIBAsmNLE
4988 { 668, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #668 = CGIBAsmNLH
4989 { 669, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo162, -1 ,nullptr }, // Inst #669 = CGIJ
4990 { 670, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo162, -1 ,nullptr }, // Inst #670 = CGIJAsm
4991 { 671, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #671 = CGIJAsmE
4992 { 672, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #672 = CGIJAsmH
4993 { 673, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #673 = CGIJAsmHE
4994 { 674, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #674 = CGIJAsmL
4995 { 675, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #675 = CGIJAsmLE
4996 { 676, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #676 = CGIJAsmLH
4997 { 677, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #677 = CGIJAsmNE
4998 { 678, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #678 = CGIJAsmNH
4999 { 679, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #679 = CGIJAsmNHE
5000 { 680, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #680 = CGIJAsmNL
5001 { 681, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #681 = CGIJAsmNLE
5002 { 682, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #682 = CGIJAsmNLH
5018 { 698, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #698 = CGRB
5019 { 699, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #699 = CGRBAsm
5020 { 700, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #700 = CGRBAsmE
5021 { 701, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #701 = CGRBAsmH
5022 { 702, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #702 = CGRBAsmHE
5023 { 703, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #703 = CGRBAsmL
5024 { 704, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #704 = CGRBAsmLE
5025 { 705, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #705 = CGRBAsmLH
5026 { 706, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #706 = CGRBAsmNE
5027 { 707, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #707 = CGRBAsmNH
5028 { 708, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #708 = CGRBAsmNHE
5029 { 709, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #709 = CGRBAsmNL
5030 { 710, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #710 = CGRBAsmNLE
5031 { 711, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #711 = CGRBAsmNLH
5032 { 712, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo165, -1 ,nullptr }, // Inst #712 = CGRJ
5033 { 713, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo165, -1 ,nullptr }, // Inst #713 = CGRJAsm
5034 { 714, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #714 = CGRJAsmE
5035 { 715, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #715 = CGRJAsmH
5036 { 716, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #716 = CGRJAsmHE
5037 { 717, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #717 = CGRJAsmL
5038 { 718, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #718 = CGRJAsmLE
5039 { 719, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #719 = CGRJAsmLH
5040 { 720, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #720 = CGRJAsmNE
5041 { 721, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #721 = CGRJAsmNH
5042 { 722, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #722 = CGRJAsmNHE
5043 { 723, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #723 = CGRJAsmNL
5044 { 724, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #724 = CGRJAsmNLE
5045 { 725, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #725 = CGRJAsmNLH
5075 { 755, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #755 = CIB
5076 { 756, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #756 = CIBAsm
5077 { 757, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #757 = CIBAsmE
5078 { 758, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #758 = CIBAsmH
5079 { 759, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #759 = CIBAsmHE
5080 { 760, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #760 = CIBAsmL
5081 { 761, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #761 = CIBAsmLE
5082 { 762, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #762 = CIBAsmLH
5083 { 763, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #763 = CIBAsmNE
5084 { 764, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #764 = CIBAsmNH
5085 { 765, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #765 = CIBAsmNHE
5086 { 766, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #766 = CIBAsmNL
5087 { 767, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #767 = CIBAsmNLE
5088 { 768, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #768 = CIBAsmNLH
5090 { 770, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo174, -1 ,nullptr }, // Inst #770 = CIJ
5091 { 771, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo174, -1 ,nullptr }, // Inst #771 = CIJAsm
5092 { 772, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #772 = CIJAsmE
5093 { 773, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #773 = CIJAsmH
5094 { 774, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #774 = CIJAsmHE
5095 { 775, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #775 = CIJAsmL
5096 { 776, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #776 = CIJAsmLE
5097 { 777, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #777 = CIJAsmLH
5098 { 778, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #778 = CIJAsmNE
5099 { 779, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #779 = CIJAsmNH
5100 { 780, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #780 = CIJAsmNHE
5101 { 781, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #781 = CIJAsmNL
5102 { 782, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #782 = CIJAsmNLE
5103 { 783, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #783 = CIJAsmNLH
5155 { 835, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #835 = CLGIB
5156 { 836, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #836 = CLGIBAsm
5157 { 837, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #837 = CLGIBAsmE
5158 { 838, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #838 = CLGIBAsmH
5159 { 839, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #839 = CLGIBAsmHE
5160 { 840, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #840 = CLGIBAsmL
5161 { 841, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #841 = CLGIBAsmLE
5162 { 842, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #842 = CLGIBAsmLH
5163 { 843, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #843 = CLGIBAsmNE
5164 { 844, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #844 = CLGIBAsmNH
5165 { 845, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #845 = CLGIBAsmNHE
5166 { 846, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #846 = CLGIBAsmNL
5167 { 847, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #847 = CLGIBAsmNLE
5168 { 848, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #848 = CLGIBAsmNLH
5169 { 849, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo162, -1 ,nullptr }, // Inst #849 = CLGIJ
5170 { 850, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo162, -1 ,nullptr }, // Inst #850 = CLGIJAsm
5171 { 851, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #851 = CLGIJAsmE
5172 { 852, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #852 = CLGIJAsmH
5173 { 853, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #853 = CLGIJAsmHE
5174 { 854, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #854 = CLGIJAsmL
5175 { 855, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #855 = CLGIJAsmLE
5176 { 856, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #856 = CLGIJAsmLH
5177 { 857, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #857 = CLGIJAsmNE
5178 { 858, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #858 = CLGIJAsmNH
5179 { 859, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #859 = CLGIJAsmNHE
5180 { 860, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #860 = CLGIJAsmNL
5181 { 861, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #861 = CLGIJAsmNLE
5182 { 862, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #862 = CLGIJAsmNLH
5198 { 878, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #878 = CLGRB
5199 { 879, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #879 = CLGRBAsm
5200 { 880, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #880 = CLGRBAsmE
5201 { 881, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #881 = CLGRBAsmH
5202 { 882, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #882 = CLGRBAsmHE
5203 { 883, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #883 = CLGRBAsmL
5204 { 884, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #884 = CLGRBAsmLE
5205 { 885, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #885 = CLGRBAsmLH
5206 { 886, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #886 = CLGRBAsmNE
5207 { 887, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #887 = CLGRBAsmNH
5208 { 888, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #888 = CLGRBAsmNHE
5209 { 889, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #889 = CLGRBAsmNL
5210 { 890, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #890 = CLGRBAsmNLE
5211 { 891, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #891 = CLGRBAsmNLH
5212 { 892, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo165, -1 ,nullptr }, // Inst #892 = CLGRJ
5213 { 893, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo165, -1 ,nullptr }, // Inst #893 = CLGRJAsm
5214 { 894, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #894 = CLGRJAsmE
5215 { 895, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #895 = CLGRJAsmH
5216 { 896, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #896 = CLGRJAsmHE
5217 { 897, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #897 = CLGRJAsmL
5218 { 898, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #898 = CLGRJAsmLE
5219 { 899, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #899 = CLGRJAsmLH
5220 { 900, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #900 = CLGRJAsmNE
5221 { 901, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #901 = CLGRJAsmNH
5222 { 902, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #902 = CLGRJAsmNHE
5223 { 903, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #903 = CLGRJAsmNL
5224 { 904, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #904 = CLGRJAsmNLE
5225 { 905, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr }, // Inst #905 = CLGRJAsmNLH
5263 { 943, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #943 = CLIB
5264 { 944, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #944 = CLIBAsm
5265 { 945, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #945 = CLIBAsmE
5266 { 946, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #946 = CLIBAsmH
5267 { 947, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #947 = CLIBAsmHE
5268 { 948, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #948 = CLIBAsmL
5269 { 949, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #949 = CLIBAsmLE
5270 { 950, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #950 = CLIBAsmLH
5271 { 951, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #951 = CLIBAsmNE
5272 { 952, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #952 = CLIBAsmNH
5273 { 953, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #953 = CLIBAsmNHE
5274 { 954, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #954 = CLIBAsmNL
5275 { 955, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #955 = CLIBAsmNLE
5276 { 956, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #956 = CLIBAsmNLH
5278 { 958, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo174, -1 ,nullptr }, // Inst #958 = CLIJ
5279 { 959, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo174, -1 ,nullptr }, // Inst #959 = CLIJAsm
5280 { 960, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #960 = CLIJAsmE
5281 { 961, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #961 = CLIJAsmH
5282 { 962, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #962 = CLIJAsmHE
5283 { 963, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #963 = CLIJAsmL
5284 { 964, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #964 = CLIJAsmLE
5285 { 965, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #965 = CLIJAsmLH
5286 { 966, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #966 = CLIJAsmNE
5287 { 967, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #967 = CLIJAsmNH
5288 { 968, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #968 = CLIJAsmNHE
5289 { 969, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #969 = CLIJAsmNL
5290 { 970, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #970 = CLIJAsmNLE
5291 { 971, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr }, // Inst #971 = CLIJAsmNLH
5297 { 977, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #977 = CLRB
5298 { 978, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #978 = CLRBAsm
5299 { 979, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #979 = CLRBAsmE
5300 { 980, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #980 = CLRBAsmH
5301 { 981, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #981 = CLRBAsmHE
5302 { 982, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #982 = CLRBAsmL
5303 { 983, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #983 = CLRBAsmLE
5304 { 984, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #984 = CLRBAsmLH
5305 { 985, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #985 = CLRBAsmNE
5306 { 986, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #986 = CLRBAsmNH
5307 { 987, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #987 = CLRBAsmNHE
5308 { 988, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #988 = CLRBAsmNL
5309 { 989, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #989 = CLRBAsmNLE
5310 { 990, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #990 = CLRBAsmNLH
5311 { 991, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr }, // Inst #991 = CLRJ
5312 { 992, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr }, // Inst #992 = CLRJAsm
5313 { 993, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #993 = CLRJAsmE
5314 { 994, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #994 = CLRJAsmH
5315 { 995, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #995 = CLRJAsmHE
5316 { 996, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #996 = CLRJAsmL
5317 { 997, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #997 = CLRJAsmLE
5318 { 998, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #998 = CLRJAsmLH
5319 { 999, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #999 = CLRJAsmNE
5320 { 1000, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1000 = CLRJAsmNH
5321 { 1001, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1001 = CLRJAsmNHE
5322 { 1002, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1002 = CLRJAsmNL
5323 { 1003, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1003 = CLRJAsmNLE
5324 { 1004, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1004 = CLRJAsmNLH
5366 { 1046, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1046 = CRB
5367 { 1047, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1047 = CRBAsm
5368 { 1048, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1048 = CRBAsmE
5369 { 1049, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1049 = CRBAsmH
5370 { 1050, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1050 = CRBAsmHE
5371 { 1051, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1051 = CRBAsmL
5372 { 1052, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1052 = CRBAsmLE
5373 { 1053, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1053 = CRBAsmLH
5374 { 1054, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1054 = CRBAsmNE
5375 { 1055, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1055 = CRBAsmNH
5376 { 1056, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1056 = CRBAsmNHE
5377 { 1057, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1057 = CRBAsmNL
5378 { 1058, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1058 = CRBAsmNLE
5379 { 1059, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1059 = CRBAsmNLH
5382 { 1062, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr }, // Inst #1062 = CRJ
5383 { 1063, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr }, // Inst #1063 = CRJAsm
5384 { 1064, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1064 = CRJAsmE
5385 { 1065, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1065 = CRJAsmH
5386 { 1066, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1066 = CRJAsmHE
5387 { 1067, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1067 = CRJAsmL
5388 { 1068, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1068 = CRJAsmLE
5389 { 1069, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1069 = CRJAsmLH
5390 { 1070, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1070 = CRJAsmNE
5391 { 1071, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1071 = CRJAsmNH
5392 { 1072, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1072 = CRJAsmNHE
5393 { 1073, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1073 = CRJAsmNL
5394 { 1074, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1074 = CRJAsmNLE
5395 { 1075, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr }, // Inst #1075 = CRJAsmNLH
5586 { 1266, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1266 = J
5587 { 1267, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1267 = JAsmE
5588 { 1268, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1268 = JAsmH
5589 { 1269, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1269 = JAsmHE
5590 { 1270, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1270 = JAsmL
5591 { 1271, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1271 = JAsmLE
5592 { 1272, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1272 = JAsmLH
5593 { 1273, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1273 = JAsmM
5594 { 1274, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1274 = JAsmNE
5595 { 1275, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1275 = JAsmNH
5596 { 1276, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1276 = JAsmNHE
5597 { 1277, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1277 = JAsmNL
5598 { 1278, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1278 = JAsmNLE
5599 { 1279, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1279 = JAsmNLH
5600 { 1280, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1280 = JAsmNM
5601 { 1281, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1281 = JAsmNO
5602 { 1282, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1282 = JAsmNP
5603 { 1283, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1283 = JAsmNZ
5604 { 1284, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1284 = JAsmO
5605 { 1285, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1285 = JAsmP
5606 { 1286, 1, 0, 4, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1286 = JAsmZ
5607 { 1287, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1287 = JG
5608 { 1288, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1288 = JGAsmE
5609 { 1289, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1289 = JGAsmH
5610 { 1290, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1290 = JGAsmHE
5611 { 1291, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1291 = JGAsmL
5612 { 1292, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1292 = JGAsmLE
5613 { 1293, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1293 = JGAsmLH
5614 { 1294, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1294 = JGAsmM
5615 { 1295, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1295 = JGAsmNE
5616 { 1296, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1296 = JGAsmNH
5617 { 1297, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1297 = JGAsmNHE
5618 { 1298, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1298 = JGAsmNL
5619 { 1299, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1299 = JGAsmNLE
5620 { 1300, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1300 = JGAsmNLH
5621 { 1301, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1301 = JGAsmNM
5622 { 1302, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1302 = JGAsmNO
5623 { 1303, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1303 = JGAsmNP
5624 { 1304, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1304 = JGAsmNZ
5625 { 1305, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1305 = JGAsmO
5626 { 1306, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1306 = JGAsmP
5627 { 1307, 1, 0, 6, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1307 = JGAsmZ
6539 { 2219, 2, 0, 4, 324, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #2219 = TABORT
gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc 1557 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
1581 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
1584 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
1640 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
1641 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
1706 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
1707 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
1729 { 174, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #174 = CATCHRET
1730 { 175, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #175 = CATCHRET_S
1731 { 176, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #176 = CLEANUPRET
1732 { 177, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #177 = CLEANUPRET_S
1735 { 180, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #180 = RETHROW_IN_CATCH
1736 { 181, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #181 = RETHROW_IN_CATCH_S
1983 { 428, 1, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #428 = BR
1984 { 429, 2, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #429 = BR_IF
1985 { 430, 1, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #430 = BR_IF_S
1986 { 431, 3, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr }, // Inst #431 = BR_ON_EXN
1987 { 432, 2, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr }, // Inst #432 = BR_ON_EXN_S
1988 { 433, 1, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #433 = BR_S
1989 { 434, 1, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo69, -1 ,nullptr }, // Inst #434 = BR_TABLE_I32
1990 { 435, 1, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo70, -1 ,nullptr }, // Inst #435 = BR_TABLE_I32_S
1991 { 436, 1, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #436 = BR_TABLE_I64
1992 { 437, 1, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo70, -1 ,nullptr }, // Inst #437 = BR_TABLE_I64_S
1993 { 438, 2, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #438 = BR_UNLESS
1994 { 439, 1, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #439 = BR_UNLESS_S
2128 { 573, 0, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr }, // Inst #573 = END_FUNCTION
2129 { 574, 0, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr }, // Inst #574 = END_FUNCTION_S
2201 { 646, 0, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #646 = FALLTHROUGH_RETURN
2202 { 647, 0, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #647 = FALLTHROUGH_RETURN_S
2671 { 1116, 1, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr }, // Inst #1116 = RETHROW
2672 { 1117, 0, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #1117 = RETHROW_S
2673 { 1118, 0, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #1118 = RETURN
2674 { 1119, 0, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #1119 = RETURN_S
2817 { 1262, 1, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1262 = THROW
2818 { 1263, 1, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1263 = THROW_S
2825 { 1270, 0, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #1270 = UNREACHABLE
2826 { 1271, 0, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #1271 = UNREACHABLE_S
gen/lib/Target/X86/X86GenInstrInfo.inc17690 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
17714 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
17717 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
17773 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
17774 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
17839 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
17840 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
17907 { 219, 2, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #219 = RETPOLINE_TCRETURN32
17908 { 220, 2, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #220 = RETPOLINE_TCRETURN64
18293 { 605, 2, 0, 0, 8, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #605 = CATCHRET
18305 { 617, 0, 0, 0, 8, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #617 = CLEANUPRET
18610 { 922, 1, 0, 0, 8, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x30c0000001ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #922 = EH_RETURN
18611 { 923, 1, 0, 0, 8, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x30c0000001ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #923 = EH_RETURN64
18612 { 924, 5, 0, 0, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #924 = EH_SjLj_LongJmp32
18613 { 925, 5, 0, 0, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #925 = EH_SjLj_LongJmp64
18616 { 928, 1, 0, 0, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #928 = EH_SjLj_Setup
18640 { 952, 2, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3a80080088ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #952 = FARJMP16i
18641 { 953, 5, 0, 0, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00000adULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #953 = FARJMP16m
18642 { 954, 2, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3a800c0108ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #954 = FARJMP32i
18643 { 955, 5, 0, 0, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc000012dULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #955 = FARJMP32m
18644 { 956, 5, 0, 0, 758, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc001002dULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #956 = FARJMP64
18803 { 1115, 1, 0, 0, 596, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0xe00000ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1115 = IRET
18804 { 1116, 0, 0, 0, 953, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x33c0e00081ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1116 = IRET16
18805 { 1117, 0, 0, 0, 953, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x33c0e00101ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1117 = IRET32
18806 { 1118, 0, 0, 0, 953, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x33c0e10001ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1118 = IRET64
18835 { 1147, 2, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1c00040009ULL, ImplicitList1, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1147 = JCC_1
18836 { 1148, 2, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x20000a2089ULL, ImplicitList1, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1148 = JCC_2
18837 { 1149, 2, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x20000e2109ULL, ImplicitList1, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1149 = JCC_4
18838 { 1150, 1, 0, 0, 628, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38c0040201ULL, ImplicitList45, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1150 = JCXZ
18839 { 1151, 1, 0, 0, 628, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38c0040401ULL, ImplicitList46, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1151 = JECXZ
18840 { 1152, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x3fc00000acULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1152 = JMP16m
18841 { 1153, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20003fc00000acULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1153 = JMP16m_NT
18842 { 1154, 1, 0, 0, 816, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x3fc00000bcULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1154 = JMP16r
18843 { 1155, 1, 0, 0, 816, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x20003fc00000bcULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1155 = JMP16r_NT
18844 { 1156, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x3fc000012cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1156 = JMP32m
18845 { 1157, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20003fc000012cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1157 = JMP32m_NT
18846 { 1158, 1, 0, 0, 816, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x3fc000013cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1158 = JMP32r
18847 { 1159, 1, 0, 0, 816, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x20003fc000013cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1159 = JMP32r_NT
18848 { 1160, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x3fc000002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1160 = JMP64m
18849 { 1161, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20003fc000002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1161 = JMP64m_NT
18850 { 1162, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc001002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1162 = JMP64m_REX
18851 { 1163, 1, 0, 0, 816, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x3fc000003cULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1163 = JMP64r
18852 { 1164, 1, 0, 0, 816, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x20003fc000003cULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1164 = JMP64r_NT
18853 { 1165, 1, 0, 0, 816, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc001003cULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1165 = JMP64r_REX
18854 { 1166, 1, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x3ac0040001ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1166 = JMP_1
18855 { 1167, 1, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x3a400a0081ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1167 = JMP_2
18856 { 1168, 1, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x3a400e0101ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1168 = JMP_4
18857 { 1169, 1, 0, 0, 628, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38c0040601ULL, ImplicitList47, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1169 = JRCXZ
19058 { 1370, 1, 0, 0, 797, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3280e80101ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1370 = LRETIL
19059 { 1371, 1, 0, 0, 797, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3280e90001ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1371 = LRETIQ
19060 { 1372, 1, 0, 0, 797, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3280e80081ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1372 = LRETIW
19061 { 1373, 0, 0, 0, 952, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x32c0e00101ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1373 = LRETL
19062 { 1374, 0, 0, 0, 928, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x32c0e10001ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1374 = LRETQ
19063 { 1375, 0, 0, 0, 952, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x32c0e00081ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1375 = LRETW
20124 { 2436, 1, 0, 0, 693, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0xe00000ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2436 = RET
20125 { 2437, 1, 0, 0, 796, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x3080e80101ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2437 = RETIL
20126 { 2438, 1, 0, 0, 796, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x3080e80101ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2438 = RETIQ
20127 { 2439, 1, 0, 0, 796, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3080e80081ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2439 = RETIW
20128 { 2440, 0, 0, 0, 847, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x30c0e00101ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2440 = RETL
20129 { 2441, 0, 0, 0, 713, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x30c0e00101ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2441 = RETQ
20130 { 2442, 0, 0, 0, 952, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x30c0e00081ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2442 = RETW
20547 { 2859, 1, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList17, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #2859 = TAILJMPd
20548 { 2860, 1, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #2860 = TAILJMPd64
20549 { 2861, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList19, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2861 = TAILJMPd64_CC
20550 { 2862, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList18, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2862 = TAILJMPd_CC
20551 { 2863, 5, 0, 0, 5, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList17, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2863 = TAILJMPm
20552 { 2864, 5, 0, 0, 5, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2864 = TAILJMPm64
20553 { 2865, 5, 0, 0, 5, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, ImplicitList6, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2865 = TAILJMPm64_REX
20554 { 2866, 1, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList17, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2866 = TAILJMPr
20555 { 2867, 1, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2867 = TAILJMPr64
20556 { 2868, 1, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, ImplicitList6, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2868 = TAILJMPr64_REX
20557 { 2869, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList17, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2869 = TCRETURNdi
20558 { 2870, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList6, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2870 = TCRETURNdi64
20559 { 2871, 3, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList19, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2871 = TCRETURNdi64cc
20560 { 2872, 3, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList18, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2872 = TCRETURNdicc
20561 { 2873, 6, 0, 0, 5, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList17, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2873 = TCRETURNmi
20562 { 2874, 6, 0, 0, 5, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList6, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2874 = TCRETURNmi64
20563 { 2875, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList17, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2875 = TCRETURNri
20564 { 2876, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList6, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2876 = TCRETURNri64
32853 { 15165, 1, 0, 0, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x31c00a00f8ULL, nullptr, ImplicitList7, OperandInfo129, -1 ,nullptr }, // Inst #15165 = XBEGIN_2
32854 { 15166, 1, 0, 0, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x31c00e0178ULL, nullptr, ImplicitList7, OperandInfo129, -1 ,nullptr }, // Inst #15166 = XBEGIN_4
gen/lib/Target/XCore/XCoreGenInstrInfo.inc 501 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
525 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
528 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
584 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
585 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
650 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
651 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
675 { 176, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #176 = BR_JT
676 { 177, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #177 = BR_JT32
677 { 178, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #178 = EH_RETURN
690 { 191, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #191 = BAU_1r
701 { 202, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #202 = BRBF_lru6
702 { 203, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #203 = BRBF_ru6
703 { 204, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #204 = BRBT_lru6
704 { 205, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #205 = BRBT_ru6
705 { 206, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #206 = BRBU_lu6
706 { 207, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #207 = BRBU_u6
707 { 208, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #208 = BRFF_lru6
708 { 209, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #209 = BRFF_ru6
709 { 210, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #210 = BRFT_lru6
710 { 211, 2, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #211 = BRFT_ru6
711 { 212, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #212 = BRFU_lu6
712 { 213, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #213 = BRFU_u6
713 { 214, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #214 = BRU_1r
719 { 220, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #220 = CLRSR_branch_lu6
720 { 221, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #221 = CLRSR_branch_u6
841 { 342, 1, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #342 = RETSP_lu6
842 { 343, 1, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #343 = RETSP_u6
858 { 359, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #359 = SETSR_branch_lu6
859 { 360, 1, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #360 = SETSR_branch_u6
894 { 395, 0, 0, 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #395 = WAITEU_0R
include/llvm/CodeGen/MachineInstr.h 699 return hasProperty(MCID::Terminator, Type);
include/llvm/MC/MCInstrDesc.h 290 bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }