1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
| //===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/SystemZMCTargetDesc.h"
#include "SystemZ.h"
#include "TargetInfo/SystemZTargetInfo.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/TargetRegistry.h"
#include <cassert>
#include <cstdint>
using namespace llvm;
#define DEBUG_TYPE "systemz-disassembler"
typedef MCDisassembler::DecodeStatus DecodeStatus;
namespace {
class SystemZDisassembler : public MCDisassembler {
public:
SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
: MCDisassembler(STI, Ctx) {}
~SystemZDisassembler() override = default;
DecodeStatus getInstruction(MCInst &instr, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &VStream,
raw_ostream &CStream) const override;
};
} // end anonymous namespace
static MCDisassembler *createSystemZDisassembler(const Target &T,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new SystemZDisassembler(STI, Ctx);
}
extern "C" void LLVMInitializeSystemZDisassembler() {
// Register the disassembler.
TargetRegistry::RegisterMCDisassembler(getTheSystemZTarget(),
createSystemZDisassembler);
}
/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
/// immediate Value in the MCInst.
///
/// @param Value - The immediate Value, has had any PC adjustment made by
/// the caller.
/// @param isBranch - If the instruction is a branch instruction
/// @param Address - The starting address of the instruction
/// @param Offset - The byte offset to this immediate in the instruction
/// @param Width - The byte width of this immediate in the instruction
///
/// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
/// called then that function is called to get any symbolic information for the
/// immediate in the instruction using the Address, Offset and Width. If that
/// returns non-zero then the symbolic information it returns is used to create
/// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
/// returns zero and isBranch is true then a symbol look up for immediate Value
/// is done and if a symbol is found an MCExpr is created with that, else
/// an MCExpr with the immediate Value is created. This function returns true
/// if it adds an operand to the MCInst and false otherwise.
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
uint64_t Address, uint64_t Offset,
uint64_t Width, MCInst &MI,
const void *Decoder) {
const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
Offset, Width);
}
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
const unsigned *Regs, unsigned Size) {
assert(RegNo < Size && "Invalid register");
RegNo = Regs[RegNo];
if (RegNo == 0)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(RegNo));
return MCDisassembler::Success;
}
static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
}
static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
}
static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
}
static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
}
static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
}
static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16);
}
static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16);
}
static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16);
}
static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32);
}
static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32);
}
static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32);
}
static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16);
}
static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16);
}
template<unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
if (!isUInt<N>(Imm))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
template<unsigned N>
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
if (!isUInt<N>(Imm))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
return MCDisassembler::Success;
}
static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeUImmOperand<1>(Inst, Imm);
}
static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeUImmOperand<2>(Inst, Imm);
}
static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeUImmOperand<3>(Inst, Imm);
}
static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeUImmOperand<4>(Inst, Imm);
}
static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeUImmOperand<6>(Inst, Imm);
}
static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeUImmOperand<8>(Inst, Imm);
}
static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeUImmOperand<12>(Inst, Imm);
}
static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeUImmOperand<16>(Inst, Imm);
}
static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeUImmOperand<32>(Inst, Imm);
}
static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeSImmOperand<8>(Inst, Imm);
}
static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeSImmOperand<16>(Inst, Imm);
}
static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder) {
return decodeSImmOperand<32>(Inst, Imm);
}
template<unsigned N>
static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address,
bool isBranch,
const void *Decoder) {
assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
uint64_t Value = SignExtend64<N>(Imm) * 2 + Address;
if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, N / 8,
Inst, Decoder))
Inst.addOperand(MCOperand::createImm(Value));
return MCDisassembler::Success;
}
static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address,
const void *Decoder) {
return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder);
}
static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address,
const void *Decoder) {
return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder);
}
static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address,
const void *Decoder) {
return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder);
}
static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address,
const void *Decoder) {
return decodePCDBLOperand<32>(Inst, Imm, Address, true, Decoder);
}
static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address,
const void *Decoder) {
return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder);
}
static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field,
const unsigned *Regs) {
uint64_t Base = Field >> 12;
uint64_t Disp = Field & 0xfff;
assert(Base < 16 && "Invalid BDAddr12");
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(Disp));
return MCDisassembler::Success;
}
static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field,
const unsigned *Regs) {
uint64_t Base = Field >> 20;
uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
assert(Base < 16 && "Invalid BDAddr20");
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
return MCDisassembler::Success;
}
static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field,
const unsigned *Regs) {
uint64_t Index = Field >> 16;
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Index < 16 && "Invalid BDXAddr12");
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(Disp));
Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
return MCDisassembler::Success;
}
static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field,
const unsigned *Regs) {
uint64_t Index = Field >> 24;
uint64_t Base = (Field >> 20) & 0xf;
uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
assert(Index < 16 && "Invalid BDXAddr20");
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
return MCDisassembler::Success;
}
static DecodeStatus decodeBDLAddr12Len4Operand(MCInst &Inst, uint64_t Field,
const unsigned *Regs) {
uint64_t Length = Field >> 16;
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Length < 16 && "Invalid BDLAddr12Len4");
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(Disp));
Inst.addOperand(MCOperand::createImm(Length + 1));
return MCDisassembler::Success;
}
static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field,
const unsigned *Regs) {
uint64_t Length = Field >> 16;
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Length < 256 && "Invalid BDLAddr12Len8");
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(Disp));
Inst.addOperand(MCOperand::createImm(Length + 1));
return MCDisassembler::Success;
}
static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field,
const unsigned *Regs) {
uint64_t Length = Field >> 16;
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Length < 16 && "Invalid BDRAddr12");
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(Disp));
Inst.addOperand(MCOperand::createReg(Regs[Length]));
return MCDisassembler::Success;
}
static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field,
const unsigned *Regs) {
uint64_t Index = Field >> 16;
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Index < 32 && "Invalid BDVAddr12");
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(Disp));
Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index]));
return MCDisassembler::Success;
}
static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs);
}
static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs);
}
static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
}
static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
}
static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
}
static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
}
static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst &Inst,
uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDLAddr12Len4Operand(Inst, Field, SystemZMC::GR64Regs);
}
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst,
uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs);
}
static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst &Inst,
uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDRAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
}
static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDVAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
}
#include "SystemZGenDisassemblerTables.inc"
DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes,
uint64_t Address,
raw_ostream &OS,
raw_ostream &CS) const {
// Get the first two bytes of the instruction.
Size = 0;
if (Bytes.size() < 2)
return MCDisassembler::Fail;
// The top 2 bits of the first byte specify the size.
const uint8_t *Table;
if (Bytes[0] < 0x40) {
Size = 2;
Table = DecoderTable16;
} else if (Bytes[0] < 0xc0) {
Size = 4;
Table = DecoderTable32;
} else {
Size = 6;
Table = DecoderTable48;
}
// Read any remaining bytes.
if (Bytes.size() < Size)
return MCDisassembler::Fail;
// Construct the instruction.
uint64_t Inst = 0;
for (uint64_t I = 0; I < Size; ++I)
Inst = (Inst << 8) | Bytes[I];
return decodeInstruction(Table, MI, Inst, Address, this, STI);
}
|