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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/MachineInstrBuilder.h 404 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID);
417 return BuildMI(*BB, BB->end(), DL, MCID);
lib/CodeGen/CFIInstrInserter.cpp 265 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
274 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
286 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
lib/CodeGen/FEntryInserter.cpp 44 BuildMI(FirstMBB, FirstMBB.begin(), DebugLoc(),
lib/CodeGen/GCRootLowering.cpp 260 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
lib/CodeGen/InlineSpiller.cpp 945 BuildMI(MBB, std::next(MI), MI->getDebugLoc(), TII.get(TargetOpcode::KILL))
lib/CodeGen/LiveDebugVariables.cpp 1333 BuildMI(*MBB, I, getDebugLoc(), TII.get(TargetOpcode::DBG_LABEL))
lib/CodeGen/MachineInstr.cpp 2090 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
lib/CodeGen/PatchableFunction.cpp 72 auto MIB = BuildMI(FirstMBB, FirstActualI, FirstActualI->getDebugLoc(),
lib/CodeGen/SelectionDAG/FastISel.cpp 839 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown));
845 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
852 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
1051 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1072 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1308 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1418 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1424 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1430 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1455 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2058 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2082 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2109 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2132 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2156 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2177 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2201 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2220 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 1028 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1039 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6656 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1259 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
lib/CodeGen/SplitKit.cpp 517 MachineInstr *CopyMI = BuildMI(MBB, InsertBefore, DebugLoc(), Desc)
lib/CodeGen/TailDuplicator.cpp 376 BuildMI(*PredBB, PredBB->end(), PredBB->findDebugLoc(PredBB->begin()),
lib/Target/AArch64/AArch64BranchTargets.cpp 126 BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
lib/Target/AArch64/AArch64ConditionalCompares.cpp 637 BuildMI(*Head, Head->end(), TermDL, MCID)
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 135 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
145 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
155 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
508 MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRWui))
514 MIB2 = BuildMI(MBB, MBBI, DL, TII->get(AArch64::LDRXui))
574 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
586 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
624 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
656 BuildMI(MBB, MBBI, MI.getDebugLoc(),
687 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::IRG))
695 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDG))
lib/Target/AArch64/AArch64FastISel.cpp 498 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1537 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1548 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
2104 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2173 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
2410 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
2480 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2486 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2496 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
2517 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2541 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2559 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg);
3075 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
3158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
3269 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
3303 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(CallReg);
3646 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
3651 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
3933 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
5125 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
5132 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
5138 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr))
lib/Target/AArch64/AArch64FrameLowering.cpp 365 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
693 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
867 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIASP))
870 BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY))
872 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIBSP))
878 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
925 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
933 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PrologEnd))
981 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PrologEnd))
1034 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1042 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1056 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BL))
1065 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1070 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVaddrEXT))
1077 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1081 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BLR))
1090 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1103 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
1155 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
1174 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1182 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PrologEnd))
1263 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1270 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1299 BuildMI(MBB, MBBI, DL,
1304 BuildMI(
1457 BuildMI(MBB, LastPopI, DL, TII->get(AArch64::SEH_EpilogStart))
1470 BuildMI(MBB, MBB.getFirstTerminator(), DL,
1511 BuildMI(MBB, MBB.getFirstTerminator(), DL,
1559 BuildMI(MBB, MBB.getFirstTerminator(), DL, TII->get(AArch64::SEH_EpilogEnd))
1962 BuildMI(MBB, MI, DL, TII.get(AArch64::STRXpost))
1970 BuildMI(MBB, MI, DL, TII.get(AArch64::SEH_Nop))
1985 BuildMI(MBB, MI, DL, TII.get(AArch64::CFI_INSTRUCTION))
2046 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
2135 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc));
2162 BuildMI(MBB, MI, DL, TII.get(AArch64::LDRXpre))
2379 BuildMI(MBB, MBBI, DL, TII.get(AArch64::STURXi))
lib/Target/AArch64/AArch64InstrInfo.cpp 1490 BuildMI(MBB, FirstEpilogSEH, DL, TII->get(AArch64::ADRP))
1493 BuildMI(MBB, FirstEpilogSEH, DL, TII->get(AArch64::ADDXri))
2430 const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
2454 const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
2645 BuildMI(MBB, I, DL, get(AArch64::STRQpre))
2650 BuildMI(MBB, I, DL, get(AArch64::LDRQpre))
2764 BuildMI(MBB, I, DL, get(AArch64::MSR))
2797 BuildMI(MBB, InsertBefore, DebugLoc(), MCID)
2902 const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
2928 BuildMI(MBB, InsertBefore, DebugLoc(), MCID)
3033 const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
3112 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_SetFP)).setMIFlag(Flag);
3114 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_AddFP))
3123 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
5588 BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
5596 BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 764 MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingWideOpcode(Opc)))
880 MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingPairOpcode(Opc)))
1399 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1408 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
lib/Target/AArch64/AArch64SpeculationHardening.cpp 221 BuildMI(MBB, MBBI, DL, TII->get(AArch64::DSB)).addImm(0xf);
222 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ISB)).addImm(0xf);
231 BuildMI(SplitEdgeBB, SplitEdgeBB.begin(), DL, TII->get(AArch64::CSELXr))
369 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::SUBSXri))
375 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::CSINVXr))
392 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::ADDXri))
398 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::ANDXrs))
404 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::ADDXri))
450 BuildMI(MBB, MBBI, MI.getDebugLoc(),
575 BuildMI(MBB, MBBI, MI.getDebugLoc(),
596 BuildMI(MBB, MBBI, DL, TII->get(AArch64::HINT)).addImm(0x14);
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 352 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead),
443 MachineInstrBuilder MILit = BuildMI(MBB, I, I->getDebugLoc(),
523 BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
554 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(R600::CF_PUSH_EG))
571 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
588 BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_END_LOOP))
596 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
610 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
625 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
644 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
652 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
662 BuildMI(MBB, MI, DL, getHWInstrDesc(CF_END));
665 BuildMI(MBB, I, DL, TII->get(R600::PAD));
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 292 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
lib/Target/AMDGPU/R600ISelLowering.cpp 311 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
379 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
386 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
394 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP))
406 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP_COND))
420 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP_COND))
448 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
lib/Target/AMDGPU/SIFixupVectorISel.cpp 186 NewGlob = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcd));
lib/Target/AMDGPU/SIFrameLowering.cpp 106 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFSET))
126 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFEN))
230 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_B32)).
234 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_B32)).
lib/Target/AMDGPU/SIISelLowering.cpp 3137 BuildMI(*LoopBB, LoopBB->begin(), DL, TII->get(AMDGPU::S_SETREG_IMM32_B32))
3150 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32))
3153 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3231 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3259 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
3355 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3366 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3421 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3450 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3524 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3531 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3535 BuildMI(MBB, I, DL, MovRelDesc)
3558 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3564 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3568 BuildMI(*LoopBB, InsPt, DL, MovRelDesc)
10800 BuildMI(*Pre, Pre->getFirstTerminator(), DebugLoc(),
10804 BuildMI(*Exit, Exit->getFirstNonDebugInstr(), DebugLoc(),
lib/Target/AMDGPU/SIInsertSkips.cpp 168 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP_DONE))
179 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)).addImm(0);
331 BuildMI(SrcMBB, InsPt, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
520 BuildMI(*BI, I, MI.getDebugLoc(), TII->get(AMDGPU::S_BRANCH))
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1581 BuildMI(*MBB, I, I->getDebugLoc(), TII->get(AMDGPU::S_DCACHE_WB));
1596 BuildMI(EntryBB, EntryBB.getFirstNonPHI(), DebugLoc(),
1600 BuildMI(EntryBB, EntryBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
lib/Target/AMDGPU/SIInstrInfo.cpp 557 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
583 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
603 BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32))
1077 BuildMI(MBB, MI, DL, OpDesc)
1095 auto MIB = BuildMI(MBB, MI, DL, get(Opcode));
1334 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP))
1354 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::S_ENDPGM)).addImm(0);
1356 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::SI_RETURN_TO_EPILOG));
1792 BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
1796 BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
1802 BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32))
1806 BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32))
4397 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(&LoopBB);
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 938 BuildMI(*MBB, CI.Paired, DL, CopyDesc)
941 MachineInstr *Copy1 = BuildMI(*MBB, CI.Paired, DL, CopyDesc)
1019 BuildMI(*MBB, CI.Paired, DL, Write2Desc)
1077 BuildMI(*MBB, CI.Paired, DL, CopyDesc)
1080 MachineInstr *Copy1 = BuildMI(*MBB, CI.Paired, DL, CopyDesc)
1127 BuildMI(*MBB, CI.Paired, DL, CopyDesc)
1130 MachineInstr *Copy1 = BuildMI(*MBB, CI.Paired, DL, CopyDesc)
1189 BuildMI(*MBB, CI.Paired, DL, CopyDesc)
1192 MachineInstr *Copy1 = BuildMI(*MBB, CI.Paired, DL, CopyDesc)
1319 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode))
lib/Target/AMDGPU/SILowerControlFlow.cpp 249 MachineInstr *NewBr = BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
326 BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
lib/Target/AMDGPU/SIMemoryLegalizer.cpp 729 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_WBINVL1));
841 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(WaitCntImmediate);
873 BuildMI(MBB, MI, DL, TII->get(Flush));
969 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL0_INV));
970 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL1_INV));
979 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL0_INV));
1107 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(WaitCntImmediate);
1112 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT_VSCNT))
lib/Target/AMDGPU/SIRegisterInfo.cpp 595 BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
715 MIB = BuildMI(*MBB, MI, DL, Desc)
843 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE))
lib/Target/ARC/ARCFrameLowering.cpp 149 BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9))
160 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK));
161 BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6))
165 BuildMI(MBB, MBBI, dl, TII->get(ARC::BL))
174 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK));
201 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
209 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
218 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
231 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
295 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(ARC::BL))
309 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(ARC::POP_S_BLINK));
313 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(ARC::LD_AB_rs9))
330 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(Opc))
lib/Target/ARC/ARCInstrInfo.cpp 315 BuildMI(MBB, I, dl, get(ARC::ST_rs9))
342 BuildMI(MBB, I, dl, get(ARC::LD_rs9))
lib/Target/ARC/ARCRegisterInfo.cpp 75 BuildMI(MBB, II, dl, TII.get(AddOpc))
106 BuildMI(MBB, II, dl, TII.get(MI.getOpcode()))
114 BuildMI(MBB, II, dl,
lib/Target/ARM/ARMBaseInstrInfo.cpp 796 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
1043 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
1054 BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
1061 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
1068 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off))
1079 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
1087 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
1095 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
1109 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
1116 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
1124 auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32));
1138 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
1145 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
1163 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
1170 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
1185 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
1326 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1334 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA))
1381 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1404 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1420 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1524 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1529 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1534 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1539 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
lib/Target/ARM/ARMBaseRegisterInfo.cpp 469 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
lib/Target/ARM/ARMConstantIslandPass.cpp 531 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
598 MachineInstr *CPEMI = BuildMI(*JumpTableBB, JumpTableBB->begin(),
2296 BuildMI(*MBB, MI_JT, MI->getDebugLoc(), TII->get(Opc))
lib/Target/ARM/ARMExpandPseudoInsts.cpp 479 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
590 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
667 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
752 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
847 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
879 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
1182 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1199 BuildMI(MBB, MBBI, dl,
1427 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1433 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1458 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
1513 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1553 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1589 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1620 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1932 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH))
1937 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL));
1940 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD))
1947 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL));
lib/Target/ARM/ARMFastISel.cpp 314 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
341 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
367 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
387 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1141 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1266 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1278 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1289 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1316 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1327 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1340 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1452 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1464 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1652 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1947 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2039 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2169 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2265 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2406 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2569 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
lib/Target/ARM/ARMFrameLowering.cpp 262 BuildMI(MBB, std::next(Info.I), dl,
537 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
548 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
605 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
612 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
647 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
671 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
693 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1263 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1278 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1291 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
lib/Target/ARM/ARMISelLowering.cpp 9981 BuildMI(*BB, Pos, dl, TII->get(StOpc))
10222 BuildMI(*BB, BB->end(), dl,
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 799 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
811 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
836 MachineInstrBuilder MIB = BuildMI(MBB, InsertBefore, DL,
1317 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1441 BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1541 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
1628 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1637 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1698 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1706 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1984 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX))
2329 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
2343 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
lib/Target/ARM/Thumb1FrameLowering.cpp 186 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
199 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
263 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
291 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
311 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
318 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
360 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
390 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
638 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
721 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
727 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
743 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
753 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
768 MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
773 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
780 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
786 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
852 BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
904 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
1003 BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
1010 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
lib/Target/ARM/Thumb1InstrInfo.cpp 68 BuildMI(MBB, I, DL, get(ARM::tPUSH))
71 BuildMI(MBB, I, DL, get(ARM::tPOP))
96 BuildMI(MBB, I, DL, get(ARM::tSTRspi))
lib/Target/ARM/Thumb2ITBlockPass.cpp 214 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
lib/Target/ARM/Thumb2InstrInfo.cpp 149 BuildMI(MBB, I, DL, get(ARM::t2STRi12))
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
208 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
lib/Target/ARM/ThumbRegisterInfo.cpp 75 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
94 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
lib/Target/AVR/AVRExpandPseudoInsts.cpp 63 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
lib/Target/AVR/AVRFrameLowering.cpp 64 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
80 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
87 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
90 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
171 BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr))
265 BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr))
333 BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
336 BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
340 BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
lib/Target/AVR/AVRInstrInfo.cpp 152 BuildMI(MBB, MI, DL, get(Opcode))
355 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
357 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(AVR::RJMPk))
lib/Target/AVR/AVRRegisterInfo.cpp 230 BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
lib/Target/AVR/AVRRelaxMemOperations.cpp 54 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
lib/Target/BPF/BPFInstrInfo.cpp 78 BuildMI(*BB, MI, dl, get(LdOpc))
81 BuildMI(*BB, MI, dl, get(StOpc))
92 BuildMI(*BB, MI, dl, get(BPF::LDW))
94 BuildMI(*BB, MI, dl, get(BPF::STW))
99 BuildMI(*BB, MI, dl, get(BPF::LDH))
101 BuildMI(*BB, MI, dl, get(BPF::STH))
106 BuildMI(*BB, MI, dl, get(BPF::LDB))
108 BuildMI(*BB, MI, dl, get(BPF::STB))
134 BuildMI(MBB, I, DL, get(BPF::STD))
139 BuildMI(MBB, I, DL, get(BPF::STW32))
lib/Target/Hexagon/HexagonConstExtenders.cpp 1597 BuildMI(MBB, At, dl, HII->get(RegOpc))
1604 BuildMI(MBB, At, dl, HII->get(RegOpc))
1618 BuildMI(MBB, At, dl, HII->get(NewOpc))
1627 MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(RegOpc));
1673 MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(RegOpc));
1731 BuildMI(MBB, At, dl, HII->get(IdxOpc))
1764 BuildMI(MBB, At, dl, HII->get(TargetOpcode::COPY))
1788 BuildMI(MBB, At, dl, HII->get(NewOpc))
1799 MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(IdxOpc));
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 722 MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, HII->get(COpc));
743 BuildMI(*ToB, At, DL, D)
908 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, HII->get(Hexagon::J2_jump))
914 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, HII->get(Hexagon::J2_jumpt))
923 MachineInstrBuilder MIB = BuildMI(*FP.SplitB, FP.SplitB->end(), DL, D);
934 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, HII->get(Hexagon::J2_jump))
lib/Target/Hexagon/HexagonExpandCondsets.cpp 645 MIB = BuildMI(B, At, DL, HII->get(Opc))
650 MIB = BuildMI(B, At, DL, HII->get(Opc))
873 MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc));
lib/Target/Hexagon/HexagonFixupHwLoops.cpp 191 MIB = BuildMI(*MBB, MII, DL, TII->get(newOp));
lib/Target/Hexagon/HexagonFrameLowering.cpp 636 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
671 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
719 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
754 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
766 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
913 BuildMI(MBB, At, DL, CFID)
917 BuildMI(MBB, At, DL, CFID)
921 BuildMI(MBB, At, DL, CFID)
967 BuildMI(MBB, At, DL, CFID)
982 BuildMI(MBB, At, DL, CFID)
986 BuildMI(MBB, At, DL, CFID)
1252 BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1310 DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1323 DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1611 BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1763 BuildMI(B, It, DL, HII.get(StoreOpc))
1774 BuildMI(B, It, DL, HII.get(StoreOpc))
1845 BuildMI(B, It, DL, HII.get(StoreOpc))
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1251 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart)
1263 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r))
1266 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_i))
1280 BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart);
lib/Target/Hexagon/HexagonInstrInfo.cpp 901 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
905 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
909 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
913 BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
917 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
929 BuildMI(MBB, I, DL, get(Opc))
941 BuildMI(MBB, I, DL, get(Opc))
1540 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
4396 NewMI = BuildMI(B, I, DL, get(insn));
lib/Target/Hexagon/HexagonNewValueJump.cpp 692 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
698 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
lib/Target/Hexagon/HexagonVExtract.cpp 133 BuildMI(DefB, At, DefI->getDebugLoc(), HII->get(StoreOpc))
lib/Target/Lanai/LanaiFrameLowering.cpp 113 BuildMI(MBB, MBBI, DL, LII.get(Lanai::SW_RI))
lib/Target/Lanai/LanaiInstrInfo.cpp 62 BuildMI(MBB, Position, DL, get(Lanai::SW_RI))
lib/Target/Lanai/LanaiMemAluCombiner.cpp 259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc));
lib/Target/MSP430/MSP430BranchSelector.cpp 196 MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::JCC))
204 MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::Bi)).addMBB(DestBB);
lib/Target/MSP430/MSP430FrameLowering.cpp 66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
199 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
lib/Target/MSP430/MSP430InstrInfo.cpp 52 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
56 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
79 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
83 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
lib/Target/Mips/Mips16FrameLowering.cpp 67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
82 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
lib/Target/Mips/Mips16InstrInfo.cpp 90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
123 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
224 MIB = BuildMI(MBB, I, DL, get(Opc));
267 MIB = BuildMI(MBB, I, DL, get(Opc));
455 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
468 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
lib/Target/Mips/MipsBranchExpansion.cpp 340 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
387 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg);
459 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW))
523 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP));
582 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD))
656 BuildMI(*LongBrMBB, Pos, DL,
lib/Target/Mips/MipsConstantIslandPass.cpp 568 BuildMI(*BB, InsAt, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY))
lib/Target/Mips/MipsDelaySlotFiller.cpp 666 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
lib/Target/Mips/MipsFastISel.cpp 211 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
855 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
979 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
lib/Target/Mips/MipsISelLowering.cpp 1274 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1526 BuildMI(*BB, II, DL, TII->get(AtomicOp))
1764 BuildMI(*BB, II, DL, TII->get(AtomicOp))
lib/Target/Mips/MipsInstrInfo.cpp 61 BuildMI(MBB, MI, DL, get(Mips::NOP));
638 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
lib/Target/Mips/MipsSEFrameLowering.cpp 439 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
473 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
478 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
489 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
494 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
500 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
521 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
535 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
758 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
lib/Target/Mips/MipsSEISelLowering.cpp 3070 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3139 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
lib/Target/Mips/MipsSEInstrInfo.cpp 132 BuildMI(MBB, I, DL, get(Mips::WRDSP))
137 BuildMI(MBB, I, DL, get(Mips::CTCMSA))
174 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
319 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
404 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
682 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
685 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
697 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
731 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
732 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
lib/Target/PowerPC/PPCBranchSelector.cpp 342 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
346 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2);
349 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2);
351 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
353 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
355 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
357 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
363 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
lib/Target/PowerPC/PPCEarlyReturn.cpp 80 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
92 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
106 BuildMI(
lib/Target/PowerPC/PPCExpandISEL.cpp 426 BuildMI(*(IsFalseBlockRequired ? FalseBlock : MBB),
458 BuildMI(*TrueBlock, TrueBlockI, dl,
483 BuildMI(*FalseBlock, FalseBlockI, dl,
lib/Target/PowerPC/PPCFastISel.cpp 687 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
699 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
722 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
796 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
1419 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1494 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1654 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
1660 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1792 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1861 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1863 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
lib/Target/PowerPC/PPCFrameLowering.cpp 981 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
1010 BuildMI(MBB, MBBI, dl, StoreInst)
1015 BuildMI(MBB, MBBI, dl, StoreInst)
1020 BuildMI(MBB, MBBI, dl, StoreInst)
1027 BuildMI(MBB, StackUpdateLoc, dl, StoreInst)
1035 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
1117 BuildMI(MBB, StackUpdateLoc, dl, TII.get(PPC::STD))
1152 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1163 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1174 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1190 BuildMI(MBB, MBBI, dl, StoreInst)
1195 BuildMI(MBB, MBBI, dl, StoreInst)
1200 BuildMI(MBB, MBBI, dl, StoreInst)
1215 BuildMI(MBB, MBBI, dl, StoreInst)
1220 BuildMI(MBB, MBBI, dl, StoreInst)
1225 BuildMI(MBB, MBBI, dl, StoreInst)
1253 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1261 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1270 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1279 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1288 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1306 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1342 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1352 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1364 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1556 BuildMI(MBB, MBBI, dl, AddInst)
1692 BuildMI(MBB, StackUpdateLoc, dl, MTLRInst).addReg(ScratchReg);
1713 BuildMI(MBB, MBBI, dl, AddInst)
1738 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1743 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1747 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1751 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1756 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1760 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 408 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
422 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
444 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
448 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
459 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
474 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
lib/Target/PowerPC/PPCInstrInfo.cpp 484 BuildMI(MBB, MI, DL, get(Opcode));
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 219 BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),
223 BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),
lib/Target/PowerPC/PPCRegisterInfo.cpp 679 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
802 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
879 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 112 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
130 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
lib/Target/RISCV/RISCVFrameLowering.cpp 152 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
171 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
187 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
201 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
273 BuildMI(MBB, LastFrameDestroy, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
288 BuildMI(MBB, std::next(I), DL,
305 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
319 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
lib/Target/RISCV/RISCVInstrInfo.cpp 131 BuildMI(MBB, I, DL, get(Opcode))
401 BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
lib/Target/Sparc/DelaySlotFiller.cpp 128 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
146 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
155 BuildMI(MBB, ++J, MI->getDebugLoc(),
lib/Target/Sparc/LeonPasses.cpp 53 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
145 BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
149 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
lib/Target/Sparc/SparcFrameLowering.cpp 163 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
168 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
176 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
lib/Target/Sparc/SparcInstrInfo.cpp 410 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
413 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
416 BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0)
419 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
422 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
427 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
lib/Target/Sparc/SparcRegisterInfo.cpp 189 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
lib/Target/SystemZ/SystemZFrameLowering.cpp 183 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
375 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
397 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
407 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
412 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
425 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
468 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
lib/Target/SystemZ/SystemZInstrInfo.cpp 833 BuildMI(MBB, MBBI, DL, get(SystemZ::TMLH))
881 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
1020 MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1048 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1063 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1078 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1093 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1104 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1131 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1142 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1191 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 329 BuildMI(*Header, InsertPos, Header->findDebugLoc(InsertPos),
361 MachineInstr *End = BuildMI(MBB, InsertPos, MBB.findPrevDebugLoc(InsertPos),
408 MachineInstr *Begin = BuildMI(MBB, InsertPos, MBB.findDebugLoc(InsertPos),
429 BuildMI(*AfterLoop, InsertPos, EndDL, TII.get(WebAssembly::END_LOOP));
577 BuildMI(*Header, InsertPos, Header->findDebugLoc(InsertPos),
618 BuildMI(*Cont, InsertPos, Bottom->findBranchDebugLoc(),
1149 BuildMI(*NestedCont, NestedCont->begin(), RangeEnd->getDebugLoc(),
1265 BuildMI(MF.back(), MF.back().end(),
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 869 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
1261 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
1289 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1304 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1348 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1355 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 132 BuildMI(MBB, InsertStore, DL, TII->get(WebAssembly::GLOBAL_SET_I32))
lib/Target/X86/X86AvoidTrailingCall.cpp 101 BuildMI(*LastRealInstr->getParent(), MBBI, LastRealInstr->getDebugLoc(),
lib/Target/X86/X86CondBrFolding.cpp 233 BuildMI(*MBB, UncondBrI, MBB->findDebugLoc(UncondBrI), TII->get(X86::JMP_1))
260 BuildMI(*MBB, UncondBrI, MBB->findDebugLoc(UncondBrI), TII->get(X86::JMP_1))
322 BuildMI(*RootMBB, UncondBrI, RootMBB->findDebugLoc(UncondBrI),
327 BuildMI(*RootMBB, UncondBrI, RootMBB->findDebugLoc(UncondBrI),
lib/Target/X86/X86ExpandPseudo.cpp 99 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr))
113 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
128 BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64))
245 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
262 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
267 BuildMI(MBB, MBBI, DL,
272 BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
303 BuildMI(MBB, MBBI, DL,
313 MIB = BuildMI(MBB, MBBI, DL,
316 MIB = BuildMI(MBB, MBBI, DL,
324 BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
326 BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
327 MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL));
362 MachineInstr *NewInstr = BuildMI(MBB, MBBI, DL, TII->get(ActualOpc));
lib/Target/X86/X86FastISel.cpp 648 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, Desc);
684 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
1278 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1282 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDbgLoc, TII.get(CompareImmOpc))
1418 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDbgLoc, TII.get(CompareOpc))
1694 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1700 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1725 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc))
1734 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1748 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1770 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
1773 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1948 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1974 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2080 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2116 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
2334 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
2793 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II), AM)
2800 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TRAP));
3313 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
3491 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc))
3508 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc));
3541 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
3585 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3995 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
lib/Target/X86/X86FixupLEAs.cpp 135 BuildMI(MBB, MBBI, MI.getDebugLoc(),
lib/Target/X86/X86FlagsCopyLowering.cpp 770 BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg);
lib/Target/X86/X86FloatingPoint.cpp 240 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
250 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
847 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
878 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
936 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
1359 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1480 BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0));
1677 Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
lib/Target/X86/X86FrameLowering.cpp 292 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
331 BuildMI(MBB, MBBI, DL, TII.get(Opc))
456 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
791 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
793 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
830 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1088 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1110 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1129 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1153 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1202 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1217 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1251 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1256 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1308 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1331 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1360 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1378 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1402 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1412 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1422 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1456 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1472 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1500 BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
1729 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
2106 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
3222 addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),
lib/Target/X86/X86ISelLowering.cpp30173 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
30174 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
lib/Target/X86/X86IndirectBranchTracking.cpp 80 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(EndbrOpcode));
lib/Target/X86/X86InstrInfo.cpp 659 BuildMI(MBB, I, DL, get(X86::MOV32ri))
799 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
864 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2461 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2591 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2594 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3257 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3951 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3958 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4721 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
lib/Target/X86/X86PadShortFunction.cpp 208 BuildMI(*MBB, MBBI, DL, TSM.getInstrInfo()->get(X86::NOOP));
lib/Target/X86/X86SpeculativeLoadHardening.cpp 460 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::LFENCE));
591 BuildMI(*MBB, InsertPt, DebugLoc(), TII->get(X86::LFENCE));
1148 auto CheckI = BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::CMP64ri32))
1167 auto CheckI = BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::CMP64rr))
lib/Target/X86/X86VZeroUpper.cpp 181 BuildMI(MBB, I, dl, TII->get(X86::VZEROUPPER));
lib/Target/X86/X86WinAllocaExpander.cpp 220 BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
234 BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
lib/Target/XCore/XCoreFrameLowering.cpp 66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
264 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
289 BuildMI(MBB, MBBI, dl, TII.get(Opcode))
372 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg);
373 BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg);
386 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
401 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
lib/Target/XCore/XCoreInstrInfo.cpp 351 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
374 BuildMI(MBB, I, DL, get(XCore::STWFI))
lib/Target/XCore/XCoreRegisterInfo.cpp 76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
146 BuildMI(MBB, II, dl, TII.get(NewOpcode))
189 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))