|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenGICombiner.inc 101 MachineBasicBlock *MBB = MI.getParent();
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 1020 MachineFunction &MF = *I.getParent()->getParent();
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc 439 MachineFunction &MF = *I.getParent()->getParent();
gen/lib/Target/ARM/ARMGenGlobalISel.inc 808 MachineFunction &MF = *I.getParent()->getParent();
gen/lib/Target/Mips/MipsGenGlobalISel.inc 633 MachineFunction &MF = *I.getParent()->getParent();
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 279 MachineFunction &MF = *I.getParent()->getParent();
gen/lib/Target/X86/X86GenGlobalISel.inc 772 MachineFunction &MF = *I.getParent()->getParent();
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 549 MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent();
766 OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
include/llvm/CodeGen/GlobalISel/RegBankSelect.h 217 : Instr.getParent()->end();
221 return *Instr.getParent();
include/llvm/CodeGen/MachineBasicBlock.h 614 assert((I == end() || I->getParent() == this) &&
621 assert((I == end() || I->getParent() == this) &&
630 assert((I == end() || I->getParent() == this) &&
640 assert((I == instr_end() || I->getParent() == this) &&
930 assert(I == BB->end() || I->getParent() == BB);
include/llvm/CodeGen/MachineInstrBuilder.h 539 : MBB(*MI->getParent()), Begin(MI),
include/llvm/CodeGen/MachineInstrBundle.h 119 InstrE = MI.getParent()->instr_end();
include/llvm/CodeGen/SlotIndexes.h 519 return MI->getParent();
546 assert(MI.getParent() != nullptr && "Instr must be added to function.");
include/llvm/Transforms/Utils/SSAUpdaterImpl.h 409 BBMap[PHI->getParent()]->PHITag = PHI;
432 if (!IncomingPHIVal || IncomingPHIVal->getParent() != PredInfo->BB)
455 BlkT *BB = PHI->getParent();
lib/CodeGen/BranchFolding.cpp 420 MachineBasicBlock &OldMBB = *OldInst->getParent();
842 MachineBasicBlock *MBB = MBBIStartPos->getParent();
lib/CodeGen/BranchRelaxation.cpp 227 MachineBasicBlock *OrigBB = MI.getParent();
302 MachineBasicBlock *MBB = MI.getParent();
439 MachineBasicBlock *MBB = MI.getParent();
lib/CodeGen/CalcSpillWeights.cpp 226 if (mi->getParent() != mbb) {
227 mbb = mi->getParent();
lib/CodeGen/EarlyIfConversion.cpp 272 if (!DefMI || DefMI->getParent() != Head)
275 LLVM_DEBUG(dbgs() << printMBBReference(*I->getParent()) << " depends on "
lib/CodeGen/ExpandPostRAPseudos.cpp 76 MachineBasicBlock *MBB = MI->getParent();
165 TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
lib/CodeGen/GCRootLowering.cpp 270 MCSymbol *Label = InsertLabel(*CI->getParent(), RAI, CI->getDebugLoc());
lib/CodeGen/GlobalISel/CombinerHelper.cpp 135 Builder.setInsertPt(*MI.getParent(), MI);
159 Builder.setInsertPt(*MI.getParent(), MI);
239 Builder.setInsertPt(*MI.getParent(), MI);
254 Builder.setInsertPt(*MI.getParent(), MI);
327 MachineBasicBlock *InsertBB = UseMI.getParent();
337 if (InsertBB == DefMI.getParent()) {
534 assert(DefMI.getParent() == UseMI.getParent());
534 assert(DefMI.getParent() == UseMI.getParent());
539 MachineBasicBlock::const_iterator I = DefMI.getParent()->begin();
549 else if (DefMI.getParent() != UseMI.getParent())
549 else if (DefMI.getParent() != UseMI.getParent())
557 auto &MF = *MI.getParent()->getParent();
624 auto &MF = *MI.getParent()->getParent();
754 MachineBasicBlock *MBB = MI.getParent();
922 auto &MF = *MI.getParent()->getParent();
1036 auto &MF = *MI.getParent()->getParent();
1144 auto &MF = *MI.getParent()->getParent();
lib/CodeGen/GlobalISel/IRTranslator.cpp 2056 MachineBasicBlock *PhiMBB = ComponentPHIs[0]->getParent();
lib/CodeGen/GlobalISel/InstructionSelector.cpp 40 MachineBasicBlock &MBB = *I.getParent();
77 if (MI.getParent() == IntoMI.getParent() &&
77 if (MI.getParent() == IntoMI.getParent() &&
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 333 const Function &F = MI.getParent()->getParent()->getFunction();
924 MachineBasicBlock &MBB = *MI.getParent();
1768 MachineBasicBlock &MBB = *MI.getParent();
2723 MachineBasicBlock *MBB = MI.getParent();
3252 MachineBasicBlock &MBB = *MI.getParent();
lib/CodeGen/GlobalISel/Localizer.cpp 101 InsertMBB = MIUse.getParent();
181 MachineBasicBlock &MBB = *MI->getParent();
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 44 assert(MI.getParent() && "Instruction is not part of a basic block");
45 setMBB(*MI.getParent());
lib/CodeGen/GlobalISel/RegBankSelect.cpp 451 MappingCost Cost(MBFI ? MBFI->getBlockFreq(MI.getParent()) : 1);
704 MachineBasicBlock *NextInstBB = MII->getParent();
750 MachineBasicBlock::iterator It = MI.getParent()->getFirstNonPHI();
751 if (It != MI.getParent()->end())
767 addInsertPoint(Pred, *MI.getParent());
786 auto REnd = MI.getParent()->rend();
794 addInsertPoint(*MI.getParent()->begin(), true);
804 for (MachineBasicBlock::iterator It = MI, End = MI.getParent()->end();
810 MachineBasicBlock &Src = *MI.getParent();
887 return MBFI->getBlockFreq(Instr.getParent()).getFrequency();
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 780 getMI().getParent() && getMI().getMF()
lib/CodeGen/GlobalISel/Utils.cpp 55 MachineBasicBlock &MBB = *InsertPt.getParent();
117 MachineBasicBlock &MBB = *I.getParent();
lib/CodeGen/ImplicitNullChecks.cpp 522 assert(MBP.ConditionDef->getParent() == &MBB && "Should be in basic block");
688 MachineBasicBlock *MBB = NC.getMemOperation()->getParent();
lib/CodeGen/InlineSpiller.cpp 384 if (DefMBB != CopyMI.getParent() || !SrcQ.isKill())
610 Edit->rematerializeAt(*MI.getParent(), MI, NewVReg, RM, TRI);
835 MachineInstrSpan MIS(MI, MI->getParent());
906 MachineBasicBlock &MBB = *MI->getParent();
936 MachineBasicBlock &MBB = *MI->getParent();
975 MachineBasicBlock *MBB = MI->getParent();
1206 MachineBasicBlock *Block = CurrentSpill->getParent();
1255 MachineBasicBlock *Block = Spill->getParent();
1479 dbgs() << spill->getParent()->getNumber() << " ";
1496 dbgs() << Rspill->getParent()->getNumber() << " ";
lib/CodeGen/LiveDebugValues.cpp 1406 MachineBasicBlock *MBB = TR.TransferInst->getParent();
lib/CodeGen/LiveIntervals.cpp 874 getMBBEndIdx(startInst.getParent()), VN);
1431 if (MI->getParent() == MBB)
1464 assert(getMBBStartIdx(MI.getParent()) <= OldIndex &&
1465 OldIndex < getMBBEndIdx(MI.getParent()) &&
lib/CodeGen/LiveRangeShrink.cpp 103 for (MachineInstr &I : make_range(Start, Start->getParent()->end()))
lib/CodeGen/LiveVariables.cpp 62 if (Kills[i]->getParent() == MBB)
101 if (VRInfo.Kills[i]->getParent() == MBB) {
140 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
149 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
168 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
179 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
539 MachineBasicBlock *MBB = MI.getParent();
594 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
743 Kills.insert(VI.Kills[i]->getParent());
lib/CodeGen/MIRCanonicalizerPass.cpp 232 if (UseInst->getParent() != Def->getParent())
232 if (UseInst->getParent() != Def->getParent())
lib/CodeGen/MIRVRegNamerUtils.cpp 67 DoesMISideEffect |= (UI->getParent()->getParent() != MI->getParent());
67 DoesMISideEffect |= (UI->getParent()->getParent() != MI->getParent());
124 if (Def->getParent() != MBB)
136 dbgs() << "BB Name: " << Def->getParent()->getName() << "\n";
lib/CodeGen/MachineBasicBlock.cpp 111 assert(!N->getParent() && "machine instruction already in a basic block");
124 assert(N->getParent() && "machine instruction not in a basic block");
156 assert(!MI->getParent() && "MI is still in a block!");
lib/CodeGen/MachineCSE.cpp 335 const MachineBasicBlock *MBB = MI->getParent();
336 const MachineBasicBlock *CSMBB = CSMI->getParent();
457 MachineBasicBlock *BB = MI->getParent();
489 if (UseMI.getParent() == MI->getParent())
489 if (UseMI.getParent() == MI->getParent())
620 if (!isProfitableToCSE(NewReg, OldReg, CSMI->getParent(), MI)) {
672 if (CSMI->getParent() == MI->getParent()) {
672 if (CSMI->getParent() == MI->getParent()) {
lib/CodeGen/MachineInstr.cpp 153 if (MachineBasicBlock *MBB = getParent())
177 MachineBasicBlock *MBB = getParent();
660 assert(getParent() && "Not embedded in a basic block!");
661 return getParent()->remove(this);
665 assert(getParent() && "Not embedded in a basic block!");
666 return getParent()->remove_instr(this);
670 assert(getParent() && "Not embedded in a basic block!");
671 getParent()->erase(this);
675 assert(getParent() && "Not embedded in a basic block!");
676 MachineBasicBlock *MBB = getParent();
695 assert(getParent() && "Not embedded in a basic block!");
696 getParent()->erase_instr(this);
2111 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
lib/CodeGen/MachineLICM.cpp 595 << " from " << printMBBReference(*MI->getParent()) << ": "
599 MachineBasicBlock *MBB = MI->getParent();
785 B = MI.getParent();
788 B = DT->findNearestCommonDominator(B, MI.getParent());
993 !IsGuaranteedToExecute(I.getParent()))
1076 if (isExitBlock(UseMI.getParent()))
1100 if (!CurLoop->contains(UseMI.getParent()))
1264 (!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI))) {
1318 MachineBasicBlock *MBB = MI->getParent();
1452 if (MI->getParent()->getBasicBlock())
1453 dbgs() << " from " << printMBBReference(*MI->getParent());
1472 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
lib/CodeGen/MachineLoopUtils.cpp 20 MachineBasicBlock *PB = MI.getParent();
64 if (Use.getParent()->getParent() != Loop)
lib/CodeGen/MachineOutliner.cpp 1053 MachineBasicBlock *MBB = StartIt->getParent();
lib/CodeGen/MachinePipeliner.cpp 826 if (getLoopPhiReg(*PMI, PMI->getParent()) == HasPhiDef)
2072 BaseReg = getLoopPhiReg(*BaseDef, MI.getParent());
2112 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent());
2598 getPhiRegs(Phi, Phi.getParent(), InitVal, LoopVal);
2623 if (!Phi || !Phi->isPHI() || Phi->getParent() != Def->getParent())
2623 if (!Phi || !Phi->isPHI() || Phi->getParent() != Def->getParent())
2627 unsigned LoopReg = getLoopPhiReg(*Phi, Phi->getParent());
lib/CodeGen/MachineSSAUpdater.cpp 230 NewVR = GetValueInMiddleOfBlock(UseMI->getParent());
lib/CodeGen/MachineScheduler.cpp 813 << printMBBReference(*begin()->getParent()) << " ***\n";
1249 << printMBBReference(*begin()->getParent()) << " ***\n";
lib/CodeGen/MachineSink.cpp 268 MachineBasicBlock *UseBlock = UseInst->getParent();
282 MachineBasicBlock *UseBlock = UseInst->getParent();
460 if (DefMI->getParent() == MI.getParent())
460 if (DefMI->getParent() == MI.getParent())
560 MachineBasicBlock *UseBlock = UseInst.getParent();
604 if (DTChild->getIDom()->getBlock() == MI.getParent() &&
726 auto *MBB = MI.getParent();
778 MachineBasicBlock *ParentBlock = MI.getParent();
867 MachineBasicBlock *ParentBlock = MI.getParent();
997 if (!User.isDebugValue() || DT->dominates(TargetBlock, User.getParent()))
1001 if (User.getParent() == MI.getParent())
1001 if (User.getParent() == MI.getParent())
lib/CodeGen/MachineTraceMetrics.cpp 831 updateDepth(Start->getParent(), *Start, RegUnits);
lib/CodeGen/ModuloSchedule.cpp 342 if (O.getParent()->getParent() != MBB)
356 if (I->getParent()->getParent() != BB)
452 while (InstOp1 && InstOp1->isPHI() && InstOp1->getParent() == BB) {
473 if (InstOp1->isPHI() && InstOp1->getParent() == KernelBB)
644 if (InstOp2->isPHI() && InstOp2->getParent() == NewBB)
655 if (InstOp1->isPHI() && InstOp1->getParent() == KernelBB)
657 if (InstOp1->isPHI() && InstOp1->getParent() == NewBB)
743 if (UI->getParent()->getParent() != BB) {
795 if (I->isPHI() && I->getParent() == KernelBB) {
801 if (!MI || MI->getParent() != KernelBB || MI->isPHI())
927 BaseReg = getLoopPhiReg(*BaseDef, MI.getParent());
1087 else if (!LoopInst->isPHI() || LoopInst->getParent() != BB)
1093 else if (StageNum > PhiStage + 1 && LoopInst->getParent() == BB)
1149 if (UseMI->getParent() != BB)
1197 getPhiRegs(Phi, Phi.getParent(), InitVal, LoopVal);
1299 if (MI->getParent())
1341 if (MI.getParent() != BB) {
1359 if (Producer->getParent() != BB)
1378 while (LoopProducer->isPHI() && LoopProducer->getParent() == BB) {
1528 BB = MO->getParent()->getParent();
1563 MRI.getVRegDef(MO->getReg())->getParent() == BB;
1641 if (Use && Use->getParent() == Pred)
1684 if (Use.getParent() != BB)
1726 if (RMIStage != -1 && !AvailableStages[MI->getParent()].test(RMIStage))
1737 if (Stage == -1 || LiveStages.count(MI->getParent()) == 0 ||
1738 LiveStages[MI->getParent()].test(Stage))
1749 MI->getParent());
lib/CodeGen/PHIEliminationUtils.cpp 37 if (RI.getParent() == MBB)
lib/CodeGen/PeepholeOptimizer.cpp 490 ReachedBBs.insert(UI.getParent());
533 MachineBasicBlock *UseMBB = UseMI->getParent();
568 PHIBBs.insert(UI.getParent());
574 MachineBasicBlock *UseMBB = UseMI->getParent();
765 MachineBasicBlock *MBB = OrigPHI.getParent();
1235 BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
lib/CodeGen/ProcessImplicitDefs.cpp 97 MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
lib/CodeGen/PrologEpilogInserter.cpp 344 TFI->eliminateCallFramePseudoInstr(MF, *I->getParent(), I);
lib/CodeGen/ReachingDefAnalysis.cpp 98 unsigned MBBNumber = MI->getParent()->getNumber();
177 unsigned MBBNumber = MI->getParent()->getNumber();
lib/CodeGen/RegAllocBase.cpp 130 MI->getParent()->getParent()->getMMI().getModule()->getContext();
lib/CodeGen/RegAllocFast.cpp 331 assert(NewDV->getParent() == MBB && "dangling parent pointer");
lib/CodeGen/RegUsageInfoPropagate.cpp 66 MachineOperand::getRegMaskSize(MI.getParent()->getParent()
lib/CodeGen/RegisterCoalescer.cpp 615 if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent())
615 if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent())
833 MachineBasicBlock *MBB = DefMI->getParent();
1031 MachineBasicBlock &MBB = *CopyMI.getParent();
1068 DefMI->getParent() != Pred) {
1278 MachineBasicBlock *MBB = CopyMI->getParent();
1489 MBB->splice(std::next(NewMI.getIterator()), UseMI->getParent(), UseMI);
lib/CodeGen/RegisterScavenging.cpp 385 MachineBasicBlock &MBB = *From->getParent();
583 const MachineBasicBlock &MBB = *To->getParent();
632 MachineBasicBlock *MBB = MO.getParent()->getParent();
lib/CodeGen/SelectionDAG/FastISel.cpp 533 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
2366 FuncInfo.MBB = User->getParent();
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 970 MI->getParent()->insert(Pos, DbgMI);
1015 MI->getParent()->insert(Pos, DbgMI);
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 582 Def->getParent()->insert(std::next(InsertPos), MI);
617 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
1710 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1834 MachineBasicBlock *PHIBB = PHI->getParent();
1887 MachineBasicBlock *PHIBB = PHI->getParent();
lib/CodeGen/SplitKit.cpp 705 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
722 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
780 defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
784 VNInfo *VNI = defFromParent(0, ParentVNI, Boundary, *MI->getParent(),
804 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
858 MachineBasicBlock *MBB = MI->getParent();
1338 LLVM_DEBUG(dbgs() << " rewr " << printMBBReference(*MI->getParent())
lib/CodeGen/TailDuplicator.cpp 195 DefBB = DefMI->getParent();
222 if (UseMI->getParent() == DefBB && !UseMI->isPHI())
293 if (UseMI.getParent() != BB)
lib/CodeGen/TargetInstrInfo.cpp 132 MachineBasicBlock *MBB = Tail->getParent();
540 MachineBasicBlock *MBB = MI.getParent();
629 MachineBasicBlock &MBB = *MI.getParent();
683 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
683 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
lib/CodeGen/TwoAddressInstructionPass.cpp 276 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
347 if (DefMI.getParent() != BB || DefMI.isDebugValue())
390 if (MI->getParent() != MBB || MI->isDebugValue())
528 if (UseMI.getParent() != MBB)
1027 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
1552 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1837 MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
lib/CodeGen/VirtRegMap.cpp 410 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/AArch64/AArch64A53Fix835769.cpp 179 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 276 MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
290 MachineBasicBlock *MBB = MI.getParent();
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp 99 MachineFunction *MF = I.getParent()->getParent();
104 MachineInstr *Copy = BuildMI(*I.getParent(), I, I.getDebugLoc(),
117 MachineFunction *MF = I.getParent()->getParent();
126 BuildMI(*I.getParent(), ++I.getIterator(), I.getDebugLoc(),
lib/Target/AArch64/AArch64CondBrTuning.cpp 105 MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
137 return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc))
145 if (MI.getParent() != DefMI.getParent())
145 if (MI.getParent() != DefMI.getParent())
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 276 MachineBasicBlock *const MBB = CmpMI->getParent();
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 498 MachineFunction &MF = *MI.getParent()->getParent();
lib/Target/AArch64/AArch64FrameLowering.cpp 487 MachineBasicBlock *MBB = MBBI->getParent();
777 assert(MBBI != MI.getParent()->end() && "Expecting a valid instruction");
lib/Target/AArch64/AArch64InstrInfo.cpp 1048 MachineBasicBlock *MBB = Instr.getParent();
1144 if (To == To->getParent()->begin())
1149 if (To->getParent() != From->getParent())
1149 if (To->getParent() != From->getParent())
1153 assert(std::find_if(++To.getReverse(), To->getParent()->rend(),
1156 }) != To->getParent()->rend());
1184 assert(CmpInstr.getParent());
1405 if (MI->getParent() != CmpInstr->getParent())
1405 if (MI->getParent() != CmpInstr->getParent())
1408 if (areCFlagsAliveInSuccessors(CmpInstr->getParent()))
1419 E = CmpInstr->getParent()->instr_end();
1473 MachineBasicBlock &MBB = *MI.getParent();
3238 MachineBasicBlock &MBB = *MI.getParent();
3466 emitFrameOffset(*MI.getParent(), MI, MI.getDebugLoc(),
3603 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc)
3667 MachineBasicBlock &MBB = *Root.getParent();
3740 MachineBasicBlock &MBB = *Root.getParent();
4103 MachineBasicBlock &MBB = *Root.getParent();
4782 assert(MI.getParent() && "Incomplete machine instruciton\n");
4783 MachineBasicBlock *MBB = MI.getParent();
4810 if (DefMI->getParent() != MBB)
5375 MachineBasicBlock *MBB = MI.getParent();
5396 if (MI.getParent()->succ_empty())
lib/Target/AArch64/AArch64InstructionSelector.cpp 725 BuildMI(*I.getParent(), I, I.getDebugLoc(),
1000 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CBOpc))
1096 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::ADDXri))
1104 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::STRXui))
1117 MachineBasicBlock &MBB = *I.getParent();
1155 MachineBasicBlock &MBB = *I.getParent();
1276 assert(I.getParent() && "Instruction should be in a basic block!");
1277 assert(I.getParent()->getParent() && "Instruction should be in a function!");
1279 MachineBasicBlock &MBB = *I.getParent();
1317 assert(I.getParent() && "Instruction should be in a basic block!");
1318 assert(I.getParent()->getParent() && "Instruction should be in a function!");
1320 MachineBasicBlock &MBB = *I.getParent();
2373 MachineFunction &MF = *I.getParent()->getParent();
2751 MachineInstr &SubRegMI = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
2759 MachineInstr &SubRegMI2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
2766 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri))
2974 MachineBasicBlock &MBB = *I.getParent();
3658 MachineBasicBlock &MBB = *I.getParent();
4153 MI.getParent()->getParent()->getFunction().hasMinSize())
4342 Root.getParent()->getParent()->getParent()->getRegInfo();
4386 Root.getParent()->getParent()->getParent()->getRegInfo();
4461 Root.getParent()->getParent()->getParent()->getRegInfo();
4575 Root.getParent()->getParent()->getParent()->getRegInfo();
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 762 MachineBasicBlock *MBB = I->getParent();
858 MachineBasicBlock *MBB = I->getParent();
978 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
1018 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
1026 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
1106 MachineBasicBlock::iterator B = I->getParent()->begin();
1216 MachineBasicBlock::iterator E = I->getParent()->end();
1399 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1408 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1490 MachineBasicBlock::iterator E = I->getParent()->end();
1549 MachineBasicBlock::iterator B = I->getParent()->begin();
1550 MachineBasicBlock::iterator E = I->getParent()->end();
1632 MachineBasicBlock::iterator E = MI.getParent()->end();
1656 MachineBasicBlock::iterator E = MI.getParent()->end();
1692 MachineBasicBlock::iterator E = MI.getParent()->end();
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 156 assert(PredMBB == CondBr.getParent() &&
lib/Target/AArch64/AArch64RegisterInfo.cpp 357 MachineFunction &MF = *MI->getParent()->getParent();
438 const MachineFunction *MF = MI.getParent()->getParent();
452 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 319 for (MachineBasicBlock::iterator MII = MI, MIE = MI.getParent()->begin();
420 if (!shouldReplaceInst(MI.getParent()->getParent(), &TII->get(MI.getOpcode()),
425 MachineBasicBlock &MBB = *MI.getParent();
508 MachineBasicBlock &MBB = *MI.getParent();
540 if (!shouldReplaceInst(MI.getParent()->getParent(), &TII->get(MI.getOpcode()),
lib/Target/AArch64/AArch64StorePairSuppress.cpp 157 if (!SuppressSTP && shouldAddSTPToBlock(MI.getParent()))
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 114 MachineBasicBlock *BB = I.getParent();
220 MachineBasicBlock *BB = MO.getParent()->getParent();
300 MachineBasicBlock *BB = I.getParent();
397 MachineBasicBlock *BB = I.getParent();
438 MachineBasicBlock *BB = I.getParent();
461 MachineBasicBlock *BB = MI.getParent();
500 MachineBasicBlock *BB = MI.getParent();
561 MachineBasicBlock *BB = I.getParent();
617 MachineBasicBlock *BB = I.getParent();
717 MachineBasicBlock *BB = I.getParent();
762 MachineBasicBlock &BB = *Insert->getParent();
1034 MachineBasicBlock *BB = I.getParent();
1093 MachineBasicBlock *BB = I.getParent();
1220 MachineBasicBlock &MBB = *I.getParent();
1369 MachineBasicBlock *MBB = I.getParent();
1399 MachineBasicBlock *BB = I.getParent();
1539 MachineBasicBlock *BB = I.getParent();
1557 MachineBasicBlock *BB = I.getParent();
1616 MachineBasicBlock *BB = I.getParent();
1921 MachineBasicBlock *MBB = MI->getParent();
2003 MachineBasicBlock *MBB = MI->getParent();
2111 MachineBasicBlock *MBB = MI->getParent();
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1733 HelperBuilder.setMBB(*MI.getParent());
1772 return UseMI.getParent() == MI.getParent() &&
1772 return UseMI.getParent() == MI.getParent() &&
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 708 if (UI.getParent()->getParent() != MBB) {
718 MIE = UseInstr->getParent()->instr_end();
741 if (!Region->contains(UI.getParent()->getParent())) {
944 bool IsInside = contains(O.getParent()->getParent());
946 O.getParent()->getParent() == getEntry());
1048 bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB;
1483 MachineBasicBlock *MBB = PHI.getParent();
1528 MachineBasicBlock *MBB = PHI.getParent();
1577 MachineBasicBlock *MBB = PHI.getParent();
1612 MachineBasicBlock *DefMBB = getDefInstr(Reg)->getParent();
1614 if ((*UI).getParent()->getParent() != DefMBB) {
1979 if (DefInstr->isPHI() && DefInstr->getParent() == CodeBB && IsSingleBB) {
1995 if (IsSingleBB && DefInstr->getParent() == InnerRegion->getEntry()) {
2022 return getDefInstr(Register)->getParent() == MBB ||
2023 InnerRegion->contains(getDefInstr(Register)->getParent());
2041 (!IsSingleBB && (getDefInstr(LI)->getParent() == LRegion->getExit()))) {
2109 if (Def->getParent()->getParent() == MBB) {
2122 if (Def->getParent()->getParent() != MBB) {
2174 MachineBasicBlock *PHIDefMBB = PHIDefInstr->getParent();
2523 MachineBasicBlock *MBB = (*I).getParent();
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 1097 B.setInsertPt(*RepairInst->getParent(), RepairInst);
1447 MachineFunction *MF = MI.getParent()->getParent();
1467 MachineFunction *MF = MI.getParent()->getParent();
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 480 MachineBasicBlock *MBB = OldMI->getParent();
492 MachineBasicBlock *MBB = OldMI->getParent();
1454 reversePredicateSetter(I, *I->getParent());
lib/Target/AMDGPU/GCNDPPCombine.cpp 167 auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
404 if (OldOpndValue->getParent()->getParent() != MovMI.getParent()) {
404 if (OldOpndValue->getParent()->getParent() != MovMI.getParent()) {
437 auto UndefInst = BuildMI(*MovMI.getParent(), MovMI, MovMI.getDebugLoc(),
515 auto *BB = OrigMI.getParent();
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 201 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII.get(AMDGPU::S_NOP))
207 MachineBasicBlock::instr_iterator E = CurrCycleInstr->getParent()->instr_end();
413 return getWaitStatesSince(IsHazard, MI->getParent(),
896 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
941 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::V_NOP_e32));
1027 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1068 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1128 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 66 auto BB = Begin->getParent();
95 const auto BB = Begin->getParent();
151 auto BB = R.Begin->getParent();
189 auto BB = R.Begin->getParent();
254 auto const BBEnd = Begin->getParent()->end();
282 auto const BBEnd = R.Begin->getParent()->end();
379 auto BB = R.Begin->getParent();
lib/Target/AMDGPU/GCNRegBankReassign.cpp 552 Weight += MLI->getLoopDepth(MI.getParent()) * 10;
lib/Target/AMDGPU/GCNRegPressure.h 213 auto &MRI = (*R.begin())->getParent()->getParent()->getRegInfo();
lib/Target/AMDGPU/GCNSchedStrategy.cpp 456 if (Regions[CurRegion].first->getParent() != MBB)
509 auto *BB = I->first->getParent();
515 } while (I != E && I->first->getParent() == BB);
556 if (RegionBegin->getParent() != MBB) {
558 MBB = RegionBegin->getParent();
lib/Target/AMDGPU/R600ClauseMergePass.cpp 101 MachineBasicBlock::iterator I = CFAlu, E = CFAlu.getParent()->end();
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 397 MachineBasicBlock *MBB = InsertPos->getParent();
472 MachineBasicBlock *BB = Clause.first->getParent();
484 MachineBasicBlock *BB = Clause.first->getParent();
lib/Target/AMDGPU/R600ISelLowering.cpp 284 if (std::next(I) == I->getParent()->end())
lib/Target/AMDGPU/R600InstrInfo.cpp 989 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
997 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1026 MachineBasicBlock *MBB = MI.getParent();
1072 buildIndirectRead(MI.getParent(), MI, MI.getOperand(0).getReg(),
1079 buildIndirectWrite(MI.getParent(), MI, MI.getOperand(2).getReg(), // Value
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 202 MachineBasicBlock &MBB = *Pos->getParent();
lib/Target/AMDGPU/R600Packetizer.cpp 314 endPacket(std::next(It)->getParent(), std::next(It));
318 endPacket(MI.getParent(), MI);
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 204 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
216 if (MO.isDef() || UseMI->getParent() != MI.getParent() ||
300 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY),
309 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(Opc),
468 const MachineBasicBlock *MBBFrom = From->getParent();
469 const MachineBasicBlock *MBBTo = To->getParent();
484 MDT.properlyDominates(Clobber->getParent(), MBBTo));
498 << printMBBReference(*MI2->getParent()) << " " << *MI2);
508 << printMBBReference(*MI1->getParent()) << " " << *MI1);
515 auto *MBB = MDT.findNearestCommonDominator(MI1->getParent(),
516 MI2->getParent());
526 << printMBBReference(*MI1->getParent()) << " " << *MI1
528 << printMBBReference(*MI2->getParent()) << " to "
529 << printMBBReference(*I->getParent()) << " " << *MI2);
530 I->getParent()->splice(I, MI2->getParent(), MI2);
530 I->getParent()->splice(I, MI2->getParent(), MI2);
560 auto MBB = MI->getParent();
740 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
lib/Target/AMDGPU/SIFoldOperands.cpp 242 MachineBasicBlock *MBB = MI->getParent();
404 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
513 MachineRegisterInfo &MRI = UseMI->getParent()->getParent()->getRegInfo();
691 MachineBasicBlock &MBB = *UseMI->getParent();
1205 MachineFunction *MF = MI.getParent()->getParent();
lib/Target/AMDGPU/SIISelLowering.cpp 3102 MachineBasicBlock *MBB = MI.getParent();
3338 MachineBasicBlock *MBB = MI.getParent();
3443 MachineBasicBlock *LoopBB = InsPt->getParent();
3555 MachineBasicBlock *LoopBB = InsPt->getParent();
10390 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
10457 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
lib/Target/AMDGPU/SIInsertSkips.cpp 150 MachineBasicBlock &MBB = *MI.getParent();
185 MachineBasicBlock &MBB = *MI.getParent();
274 const MachineFunction *MF = MI.getParent()->getParent();
345 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1152 auto SWaitInst = BuildMI(*MI.getParent(), MI.getIterator(),
1167 BuildMI(*MI.getParent(), MI.getIterator(), MI.getDebugLoc(),
lib/Target/AMDGPU/SIInstrInfo.cpp 1372 MachineBasicBlock &MBB = *MI.getParent();
1567 MachineBasicBlock &MBB = *MI.getParent();
2342 UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
3060 MachineBasicBlock *MBB = MI.getParent();;
3826 MachineBasicBlock *MBB = MI.getParent();
3848 BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);
3859 MachineBasicBlock *MBB = MI->getParent();
4038 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4045 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4071 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4142 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4148 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4221 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4228 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4237 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4244 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4404 MachineBasicBlock &MBB = *MI.getParent();
4473 MachineBasicBlock &MBB = *MI.getParent();
4515 MachineFunction &MF = *MI.getParent()->getParent();
4596 MachineBasicBlock *MBB = MI.getParent();
4628 MachineBasicBlock *MBB = MI.getParent();
4692 MachineBasicBlock &MBB = *MI.getParent();
4823 MachineBasicBlock *MBB = Inst.getParent();
5035 Inst.addImplicitDefUseOperands(*Inst.getParent()->getParent());
5108 MachineBasicBlock &MBB = *Inst.getParent();
5138 MachineBasicBlock &MBB = *Inst.getParent();
5165 MachineBasicBlock &MBB = *Inst.getParent();
5231 MachineBasicBlock &MBB = *Inst.getParent();
5260 MachineBasicBlock &MBB = *Inst.getParent();
5289 MachineBasicBlock &MBB = *Inst.getParent();
5345 MachineBasicBlock &MBB = *Inst.getParent();
5415 MachineBasicBlock &MBB = *Inst.getParent();
5479 MachineBasicBlock &MBB = *Inst.getParent();
5520 MachineBasicBlock &MBB = *Inst.getParent();
5557 MachineBasicBlock &MBB = *Inst.getParent();
5656 MachineBasicBlock *MBB = Inst.getParent();
5724 SCCDefInst.getParent()->end())) {
6243 MachineBasicBlock *MBB = MI.getParent();
6498 if (UseInst.getParent() != DefBB)
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 551 MachineBasicBlock *MBB = I->getParent();
753 MachineBasicBlock *MBB = CI.I->getParent();
873 MachineBasicBlock *MBB = CI.I->getParent();
972 MachineBasicBlock *MBB = CI.I->getParent();
1039 MachineBasicBlock *MBB = CI.I->getParent();
1093 MachineBasicBlock *MBB = CI.I->getParent();
1143 MachineBasicBlock *MBB = CI.I->getParent();
1297 MachineBasicBlock *MBB = CI.I->getParent();
1362 BuildMI(*MI.getParent(), MI.getIterator(), MI.getDebugLoc(),
1373 MachineBasicBlock *MBB = MI.getParent();
1588 MachineBasicBlock *MBB = MI.getParent();
lib/Target/AMDGPU/SILowerControlFlow.cpp 160 auto EMBB = U->getParent();
181 MachineBasicBlock *MBB = MI->getParent();
199 MachineBasicBlock &MBB = *MI.getParent();
282 MachineBasicBlock &MBB = *MI.getParent();
355 MachineBasicBlock &MBB = *MI.getParent();
366 SkipAnding = Def->getParent() == MI.getParent()
366 SkipAnding = Def->getParent() == MI.getParent()
396 MachineBasicBlock &MBB = *MI.getParent();
417 MachineBasicBlock &MBB = *MI.getParent();
424 Def && Def->getParent() == &MBB ? std::next(MachineBasicBlock::iterator(Def))
450 if (!Def || Def->getParent() != MI.getParent() ||
450 if (!Def || Def->getParent() != MI.getParent() ||
lib/Target/AMDGPU/SILowerI1Copies.cpp 561 MachineBasicBlock &MBB = *MI->getParent();
602 DomBlocks.push_back(Use.getParent());
715 DomBlocks.push_back(Use.getParent());
lib/Target/AMDGPU/SIMachineScheduler.cpp 2047 << printMBBReference(*begin()->getParent()) << " ***\n";
lib/Target/AMDGPU/SIMemoryLegalizer.cpp 446 const Function &Func = MI->getParent()->getParent()->getFunction();
719 MachineBasicBlock &MBB = *MI->getParent();
763 MachineBasicBlock &MBB = *MI->getParent();
857 MachineBasicBlock &MBB = *MI->getParent();
959 MachineBasicBlock &MBB = *MI->getParent();
1013 MachineBasicBlock &MBB = *MI->getParent();
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 227 Cmp->getParent() != And->getParent())
227 Cmp->getParent() != And->getParent())
419 if (U.getParent() != SaveExec->getParent()) {
419 if (U.getParent() != SaveExec->getParent()) {
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 128 return &getParentInst()->getParent()->getParent()->getRegInfo();
504 auto MBB = MI.getParent();
912 MachineBasicBlock &MBB = *MI.getParent();
1010 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), SDWADesc);
1193 auto Copy = BuildMI(*MI.getParent(), MI.getIterator(), MI.getDebugLoc(),
lib/Target/AMDGPU/SIRegisterInfo.cpp 396 MachineBasicBlock *MBB = MI.getParent();
549 MachineBasicBlock *MBB = MI->getParent();
550 MachineFunction *MF = MI->getParent()->getParent();
580 MachineBasicBlock *MBB = MI->getParent();
624 MachineBasicBlock *MBB = MI->getParent();
625 MachineFunction *MF = MI->getParent()->getParent();
749 MachineBasicBlock *MBB = MI->getParent();
867 MachineFunction *MF = MI->getParent()->getParent();
868 MachineBasicBlock *MBB = MI->getParent();
986 MachineFunction *MF = MI->getParent()->getParent();
987 MachineBasicBlock *MBB = MI->getParent();
lib/Target/AMDGPU/SIShrinkInstructions.cpp 226 MachineFunction *MF = MI.getParent()->getParent();
488 if (!TRI.isVGPR(MRI, Y) || MovT.getParent() != MovY.getParent())
488 if (!TRI.isVGPR(MRI, Y) || MovT.getParent() != MovY.getParent())
492 auto I = std::next(MovT.getIterator()), E = MovT.getParent()->instr_end();
528 BuildMI(*MovT.getParent(), MovX->getIterator(), MovT.getDebugLoc(),
lib/Target/AMDGPU/SIWholeQuadMode.cpp 428 MachineBasicBlock *MBB = MI.getParent();
845 BuildMI(*MI->getParent(), MI, DL, TII->get(AMDGPU::COPY), Dest)
lib/Target/ARC/ARCBranchFinalize.cpp 117 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
132 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
136 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc))
lib/Target/ARC/ARCExpandPseudos.cpp 65 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg)
68 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(),
lib/Target/ARC/ARCOptAddrMode.cpp 245 Add.getParent()->insertAfter(Add.getIterator(), &Ldst);
389 if (Ldst->getParent() != To->getParent())
389 if (Ldst->getParent() != To->getParent())
392 End(Ldst->getParent()->end());
417 if (Ldst->getParent() != To->getParent())
417 if (Ldst->getParent() != To->getParent())
420 End(Ldst->getParent()->end());
lib/Target/ARC/ARCRegisterInfo.cpp 44 MachineBasicBlock &MBB = *MI.getParent();
173 MachineFunction &MF = *MI.getParent()->getParent();
lib/Target/ARM/A15SDOptimizer.cpp 512 MachineBasicBlock &MBB = *MI->getParent();
lib/Target/ARM/ARMBaseInstrInfo.cpp 148 MachineFunction &MF = *MI.getParent()->getParent();
503 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1519 MachineBasicBlock *BB = MI->getParent();
1572 MI.getParent()->erase(MI);
1615 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
2239 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2257 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
2292 if (DefMI->getParent() != MI.getParent())
2292 if (DefMI->getParent() != MI.getParent())
2487 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2917 if (UI->getParent() != CmpInstr.getParent())
2917 if (UI->getParent() != CmpInstr.getParent())
2932 B = CmpInstr.getParent()->begin();
2946 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
2946 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
2989 CmpInstr.getParent()->insert(E, MI);
3053 E = CmpInstr.getParent()->end();
3156 MachineBasicBlock *MBB = CmpInstr.getParent();
3318 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
4773 MachineBasicBlock &MBB = *MI->getParent();
4915 MI.getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4932 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5073 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
5225 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
5369 while (CmpMI != Br->getParent()->begin()) {
lib/Target/ARM/ARMBaseRegisterInfo.cpp 582 MachineFunction &MF = *MI->getParent()->getParent();
657 MachineBasicBlock &MBB = *MI.getParent();
753 MachineBasicBlock &MBB = *MI.getParent();
815 TII.getRegClass(MCID, FIOperandNum, this, *MI.getParent()->getParent());
843 auto MBB = MI->getParent();
lib/Target/ARM/ARMBasicBlockInfo.cpp 76 const MachineBasicBlock *MBB = MI->getParent();
101 << " from " << printMBBReference(*MI->getParent())
lib/Target/ARM/ARMConstantIslandPass.cpp 140 HighWaterMark = CPEMI->getParent();
887 MachineBasicBlock *OrigBB = MI->getParent();
975 const BasicBlockInfo &BBI = BBInfo[U.MI->getParent()->getNumber()];
1069 unsigned Block = MI->getParent()->getNumber();
1074 << printMBBReference(*MI->getParent()) << ": "
1215 MachineBasicBlock *UserBB = U.MI->getParent();
1237 NewWaterList.count(WaterBB) || WaterBB == U.MI->getParent()) &&
1245 if (CloserWater && WaterBB == U.MI->getParent())
1272 MachineBasicBlock *UserMBB = UserMI->getParent();
1559 MachineBasicBlock *CPEBB = CPEMI->getParent();
1623 MachineBasicBlock *MBB = MI->getParent();
1666 MachineBasicBlock *MBB = MI->getParent();
1732 BBUtils->adjustBBSize(MI->getParent(), -TII->getInstSizeInBytes(*MI));
1750 BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET))
1808 MachineBasicBlock *MBB = U.MI->getParent();
1846 MachineBasicBlock *MBB = Br.MI->getParent();
1905 MachineBasicBlock *MBB = Br.MI->getParent();
1936 MachineBasicBlock *MBB = Br.MI->getParent();
2028 if (JumpMI->getParent() != LEAMI->getParent())
2028 if (JumpMI->getParent() != LEAMI->getParent())
2110 MachineFunction::iterator MBB = JTMI->getParent()->getIterator();
2199 MachineBasicBlock *MBB = MI->getParent();
2224 if (User.MI->getIterator() == User.MI->getParent()->begin())
2373 int JTNumber = MI->getParent()->getNumber();
2383 adjustJTTargetBlockForward(MBB, MI->getParent());
lib/Target/ARM/ARMExpandPseudoInsts.cpp 471 MachineBasicBlock &MBB = *MI.getParent();
582 MachineBasicBlock &MBB = *MI.getParent();
658 MachineBasicBlock &MBB = *MI.getParent();
749 MachineBasicBlock &MBB = *MI.getParent();
1334 MachineFunction &MF = *MI.getParent()->getParent();
lib/Target/ARM/ARMHazardRecognizer.cpp 46 const MachineFunction *MF = MI->getParent()->getParent();
55 if (I != LastMI->getParent()->begin()) {
lib/Target/ARM/ARMISelLowering.cpp10695 MachineFunction *MF = MI.getParent()->getParent();
lib/Target/ARM/ARMInstrInfo.cpp 93 MachineFunction &MF = *MI->getParent()->getParent();
118 MachineBasicBlock &MBB = *MI->getParent();
lib/Target/ARM/ARMInstructionSelector.cpp 483 : MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
621 auto &MBB = *MIB->getParent();
768 auto &MBB = *MIB->getParent();
837 assert(I.getParent() && "Instruction should be in a basic block!");
838 assert(I.getParent()->getParent() && "Instruction should be in a function!");
840 auto &MBB = *I.getParent();
1141 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri))
1150 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc))
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 894 MachineBasicBlock &MBB = *LatestMI->getParent();
949 MachineInstrBuilder MIB(*Merged->getParent()->getParent(), Merged);
1214 MachineBasicBlock &MBB = *MBBI->getParent();
1234 MachineBasicBlock &MBB = *MBBI->getParent();
1278 MachineBasicBlock &MBB = *MI->getParent();
1411 MachineBasicBlock &MBB = *MI->getParent();
1524 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/ARM/ARMLowOverheadLoops.cpp 156 MachineBasicBlock *MBB = Start->getParent();
361 MachineBasicBlock *MBB = MI->getParent();
383 MachineBasicBlock *MBB = MI->getParent();
417 MachineBasicBlock *MBB = MI->getParent();
448 MachineBasicBlock *MBB = InsertPt->getParent();
469 MachineBasicBlock *MBB = End->getParent();
488 MachineBasicBlock *BB = I->getParent();
lib/Target/ARM/MLxExpansionPass.cpp 93 MachineBasicBlock *MBB = MI->getParent();
96 if (DefMI->getParent() != MBB)
121 MachineBasicBlock *MBB = MI->getParent();
123 if (UseMI->getParent() != MBB)
131 if (UseMI->getParent() != MBB)
145 MachineBasicBlock *MBB = MI->getParent();
149 if (DefMI->getParent() != MBB)
286 const MachineFunction &MF = *MI->getParent()->getParent();
lib/Target/ARM/MVEVPTBlockPass.cpp 144 while (CmpMI != MI->getParent()->begin()) {
lib/Target/ARM/Thumb1InstrInfo.cpp 135 MachineFunction &MF = *MI->getParent()->getParent();
lib/Target/ARM/Thumb2ITBlockPass.cpp 180 MachineBasicBlock::iterator E = MI->getParent()->end();
lib/Target/ARM/Thumb2InstrInfo.cpp 60 MachineBasicBlock *MBB = Tail->getParent();
223 MachineFunction &MF = *MI->getParent()->getParent();
473 MachineFunction &MF = *MI.getParent()->getParent();
493 MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
lib/Target/ARM/ThumbRegisterInfo.cpp 364 MachineBasicBlock &MBB = *MI.getParent();
432 const MachineFunction &MF = *MI.getParent()->getParent();
454 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/AVR/AVRExpandPseudoInsts.cpp 864 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/AVR/AVRISelLowering.cpp 1623 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
lib/Target/AVR/AVRRegisterInfo.cpp 135 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/BPF/BPFISelLowering.cpp 589 MachineFunction *MF = MI.getParent()->getParent();
lib/Target/BPF/BPFInstrInfo.cpp 51 MachineBasicBlock *BB = MI->getParent();
lib/Target/BPF/BPFRegisterInfo.cpp 63 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/Hexagon/HexagonBitSimplify.cpp 2024 MachineBasicBlock &B = *MI->getParent();
2047 MachineBasicBlock &B = *MI->getParent();
2095 MachineBasicBlock &B = *MI->getParent();
2136 MachineBasicBlock &B = *MI->getParent();
2266 MachineBasicBlock &B = *DefS->getParent();
2335 MachineBasicBlock &B = *MI->getParent();
2540 MachineBasicBlock &B = *MI->getParent();
2589 MachineBasicBlock &B = *MI->getParent();
3117 if (UseI->getParent() != C.LB) {
3170 if (UseI->getParent() == C.LB) {
lib/Target/Hexagon/HexagonBranchRelaxation.cpp 145 MachineBasicBlock &B = *MI.getParent();
lib/Target/Hexagon/HexagonCFGOptimizer.cpp 83 MI.getParent()->getParent()->getSubtarget().getInstrInfo();
lib/Target/Hexagon/HexagonConstExtenders.cpp 198 assert(It->getParent() == B);
1489 MachineBasicBlock *DomB = ED0.UseMI->getParent();
1494 MachineBasicBlock *MBB = ED.UseMI->getParent();
1585 MachineBasicBlock &MBB = *MI.getParent();
1703 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/Hexagon/HexagonConstPropagation.cpp 2842 MachineBasicBlock &B = *MI.getParent();
2934 MachineFunction &MF = *MI.getParent()->getParent();
2950 MachineBasicBlock &B = *MI.getParent();
3125 MachineBasicBlock &B = *BrI.getParent();
lib/Target/Hexagon/HexagonCopyToCombine.cpp 528 while (I2 != I1.getParent()->end() && I2->isDebugInstr())
533 for (MachineBasicBlock::iterator End = I1.getParent()->end(); I2 != End;
632 MachineBasicBlock *BB = InsertPt->getParent();
653 MachineBasicBlock *BB = InsertPt->getParent();
668 MachineBasicBlock *BB = InsertPt->getParent();
765 MachineBasicBlock *BB = InsertPt->getParent();
813 MachineBasicBlock *BB = InsertPt->getParent();
864 MachineBasicBlock *BB = InsertPt->getParent();
lib/Target/Hexagon/HexagonExpandCondsets.cpp 419 Defs.insert(DefI->getParent());
517 MachineFunction &MF = *DefI->getParent()->getParent();
627 MachineBasicBlock &B = *At->getParent();
669 LLVM_DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent())
698 MachineFunction &MF = *MI.getParent()->getParent();
746 MachineBasicBlock &B = *UseIt->getParent();
869 MachineBasicBlock &B = *MI.getParent();
lib/Target/Hexagon/HexagonFixupHwLoops.cpp 171 MachineBasicBlock *MBB = MII->getParent();
lib/Target/Hexagon/HexagonFrameLowering.cpp 2332 MachineBasicBlock &MB = *AI->getParent();
lib/Target/Hexagon/HexagonGenInsert.cpp 1411 MachineBasicBlock &B = *MI->getParent();
lib/Target/Hexagon/HexagonGenMux.cpp 335 MachineBasicBlock &B = *MX.At->getParent();
lib/Target/Hexagon/HexagonGenPredicate.cpp 265 MachineBasicBlock &B = *DefI->getParent();
384 MachineBasicBlock &B = *MI->getParent();
lib/Target/Hexagon/HexagonHardwareLoops.cpp 698 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
708 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
1213 MachineBasicBlock *BBDef = TCDef->getParent();
1324 MachineBasicBlock *BB = BumpI->getParent();
1325 if (CmpI->getParent() != BB)
1395 Phi->getParent(), L, LoopFeederPhi))
1443 if (Def->isPHI() && !phiMayWrapOrUnderflow(Def, EndVal, Def->getParent(),
1447 EndVal, Def->getParent(),
1465 if (TII->analyzeBranch(*MI->getParent(), TBB, FBB, Cond, false))
1590 MachineBasicBlock &B = *DI->getParent();
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 55 MachineFunction *MF = MI->getParent()->getParent();
126 MachineFunction *MF = MI->getParent()->getParent();
lib/Target/Hexagon/HexagonInstrInfo.cpp 688 : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
724 NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(),
743 BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
1022 MachineBasicBlock &MBB = *MI.getParent();
1435 MachineBasicBlock &MBB = *MI.getParent();
1576 MachineBasicBlock &B = *MI.getParent();
lib/Target/Hexagon/HexagonMachineScheduler.cpp 119 MachineBasicBlock *MBB = SU->getInstr()->getParent();
247 << printMBBReference(*begin()->getParent()) << " ***\n";
lib/Target/Hexagon/HexagonNewValueJump.cpp 340 MachineBasicBlock *Src = MI->getParent();
678 MBB->splice(jmpPos, MI.getParent(), MI);
679 MBB->splice(jmpPos, MI.getParent(), cmpInstr);
lib/Target/Hexagon/HexagonOptAddrMode.cpp 190 MI.getParent() != UseMI.getParent())
190 MI.getParent() != UseMI.getParent())
317 MI->getParent() != UseMI->getParent())
317 MI->getParent() != UseMI->getParent())
399 LLVM_DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber()
485 MachineBasicBlock *BB = OldMI->getParent();
548 MachineBasicBlock *BB = OldMI->getParent();
622 LLVM_DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent())
635 MachineBasicBlock *BB = UseMI->getParent();
749 LLVM_DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent())
lib/Target/Hexagon/HexagonRegisterInfo.cpp 188 MachineBasicBlock &MB = *MI.getParent();
243 MachineFunction &MF = *MI->getParent()->getParent();
lib/Target/Hexagon/HexagonSplitDouble.cpp 454 const MachineBasicBlock *PB = UseI->getParent();
596 MachineBasicBlock &B = *MI->getParent();
635 MachineBasicBlock &B = *MI->getParent();
707 MachineBasicBlock &B = *MI->getParent();
734 MachineBasicBlock &B = *MI->getParent();
763 MachineBasicBlock &B = *MI->getParent();
800 MachineBasicBlock &B = *MI->getParent();
920 MachineBasicBlock &B = *MI->getParent();
1101 MachineBasicBlock &B = *MI->getParent();
1181 MachineBasicBlock *B = MI->getParent();
lib/Target/Hexagon/HexagonStoreWidening.cpp 483 MachineBasicBlock *MBB = OG.back()->getParent();
lib/Target/Hexagon/HexagonVExtract.cpp 68 MachineBasicBlock &ExtB = *ExtI->getParent();
129 MachineBasicBlock &DefB = *DefI->getParent();
145 MachineBasicBlock &ExtB = *ExtI->getParent();
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 168 MachineBasicBlock &B = *MI.getParent();
1349 if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
1690 MachineBasicBlock *MBB = MI.getParent();
1829 auto *OldBB = OldPacketMIs.front()->getParent();
lib/Target/Hexagon/HexagonVectorPrint.cpp 165 MachineBasicBlock *MBB = I->getParent();
lib/Target/Hexagon/RDFGraph.cpp 1108 << printMBBReference(*MI->getParent()) << '\n';
lib/Target/Hexagon/RDFLiveness.cpp 171 return NodeAddr<StmtNode*>(IA).Addr->getCode()->getParent();
lib/Target/Lanai/LanaiInstrInfo.cpp 293 B = CmpInstr.getParent()->begin();
307 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
307 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
354 E = CmpInstr.getParent()->end();
420 MachineBasicBlock *MBB = CmpInstr.getParent();
497 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
514 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
544 if (DefMI->getParent() != MI.getParent())
544 if (DefMI->getParent() != MI.getParent())
lib/Target/Lanai/LanaiRegisterInfo.cpp 142 MachineFunction &MF = *MI.getParent()->getParent();
188 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::MOVHI), Reg)
190 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::OR_I_LO), Reg)
195 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::ADD_I_LO), Reg)
201 BuildMI(*MI.getParent(), II, DL,
238 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
lib/Target/MSP430/MSP430RegisterInfo.cpp 109 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/Mips/MicroMipsSizeReduction.cpp 459 Arguments->MI->getParent()->instr_end();
616 Arguments->MI->getParent()->instr_end();
708 MachineBasicBlock &MBB = *MI->getParent();
lib/Target/Mips/Mips16InstrInfo.cpp 147 MachineBasicBlock &MBB = *MI.getParent();
356 (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
lib/Target/Mips/Mips16RegisterInfo.cpp 80 MachineFunction &MF = *MI.getParent()->getParent();
134 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/Mips/MipsBranchExpansion.cpp 193 Iter I = Position, E = Position->getParent()->end();
401 MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
lib/Target/Mips/MipsConstantIslandPass.cpp 273 HighWaterMark = CPEMI->getParent();
802 MachineBasicBlock *MBB = MI->getParent();
851 MachineBasicBlock *OrigBB = MI.getParent();
982 unsigned Block = MI->getParent()->getNumber();
987 << printMBBReference(*MI->getParent()) << ": "
1218 MachineBasicBlock *UserMBB = UserMI->getParent();
1417 MachineBasicBlock *CPEBB = CPEMI->getParent();
1466 << " from " << printMBBReference(*MI->getParent())
1505 MachineBasicBlock *MBB = MI->getParent();
1569 MachineBasicBlock *MBB = MI->getParent();
1633 BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
lib/Target/Mips/MipsDelaySlotFiller.cpp 313 MachineFunction *MF = Filler->getParent()->getParent();
lib/Target/Mips/MipsISelLowering.cpp 3006 MachineFunction *MF = MI.getParent()->getParent();
lib/Target/Mips/MipsInstrInfo.cpp 610 auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
638 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
lib/Target/Mips/MipsInstructionSelector.cpp 231 MachineBasicBlock &MBB = *I.getParent();
lib/Target/Mips/MipsOptimizePICCall.cpp 166 MachineFunction &MF = *MI.getParent()->getParent();
280 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
lib/Target/Mips/MipsRegisterBankInfo.cpp 197 const MachineFunction &MF = *MI->getParent()->getParent();
211 const MachineFunction &MF = *MI->getParent()->getParent();
lib/Target/Mips/MipsRegisterInfo.cpp 260 MachineFunction &MF = *MI.getParent()->getParent();
lib/Target/Mips/MipsSEInstrInfo.cpp 409 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/Mips/MipsSERegisterInfo.cpp 108 ->getParent()
150 MachineFunction &MF = *MI.getParent()->getParent();
220 MachineBasicBlock &MBB = *MI.getParent();
239 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/NVPTX/NVPTXPeephole.cpp 74 auto &MBB = *Root.getParent();
89 if (!GenericAddrDef || GenericAddrDef->getParent() != &MBB ||
105 auto &MBB = *Root.getParent();
lib/Target/NVPTX/NVPTXRegisterInfo.cpp 120 MachineFunction &MF = *MI.getParent()->getParent();
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp 80 MachineFunction &MF = *MI.getParent()->getParent();
lib/Target/PowerPC/PPCBranchCoalescing.cpp 430 if (Use.isPHI() && Use.getParent() == &TargetMBB) {
462 if (DefInst->isPHI() && DefInst->getParent() == MI.getParent()) {
541 if (Use.isPHI() && Use.getParent() == SourceRegion.BranchTargetBlock) {
549 if (Use.getParent() == SourceRegion.BranchBlock) {
lib/Target/PowerPC/PPCCTRLoops.cpp 158 << printMBBReference(*BI->getParent()) << " ("
159 << BI->getParent()->getFullName() << ") instruction "
175 << printMBBReference(*BI->getParent()) << " ("
176 << BI->getParent()->getFullName() << ") instruction "
lib/Target/PowerPC/PPCExpandISEL.cpp 227 MachineBasicBlock *MBB = (*I)->getParent();
497 MachineBasicBlock *MBB = BIL.back()->getParent();
lib/Target/PowerPC/PPCFrameLowering.cpp 294 MachineBasicBlock *Entry = MI.getParent();
340 MachineFunction *MF = MI.getParent()->getParent();
386 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
390 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
395 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
399 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
404 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
408 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
412 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
lib/Target/PowerPC/PPCInstrInfo.cpp 276 if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
371 MachineFunction &MF = *MI.getParent()->getParent();
1447 MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1450 MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1453 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1469 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1477 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1485 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1503 MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1508 MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1514 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1721 for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1750 else if (MI->getParent() != CmpInstr.getParent())
1750 else if (MI->getParent() != CmpInstr.getParent())
1798 MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1913 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1983 MI->addOperand(*MI->getParent()->getParent(),
1989 MI->addOperand(*MI->getParent()->getParent(),
2133 auto &MBB = *MI.getParent();
2143 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2311 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2319 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2325 assert(!MI.getParent()->getParent()->getRegInfo().isSSA() &&
2328 MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI;
2346 MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
2456 StartMI.getParent()->getParent()->getRegInfo();
2461 assert((StartMI.getParent() == EndMI.getParent()) &&
2461 assert((StartMI.getParent() == EndMI.getParent()) &&
2490 MachineBasicBlock::reverse_iterator E = EndMI.getParent()->rend();
2555 MachineFunction *MF = MI.getParent()->getParent();
2754 MachineFunction *MF = MI.getParent()->getParent();
3453 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3635 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3717 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3801 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3810 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
4169 MF(Loop->getParent()->getParent()),
lib/Target/PowerPC/PPCMIPeephole.cpp 225 uint64_t CurrBlockFreq = MBFI->getBlockFreq(MI->getParent()).getFrequency();
231 if (CurrBlockFreq > EntryFreq || MPDT->dominates(MI->getParent(), Entry))
786 MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI)
922 if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) {
957 if (CMPI->getParent() != &BB)
1017 if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI)
1283 if (Inst->getParent() != &MBB2)
1440 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 68 if (DefMI->getParent() == NewMBB ||
98 MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
119 MachineBasicBlock *MBB = OrigBranch->getParent();
120 if (SplitBefore->getParent() != MBB || SplitCond->getParent() != MBB)
120 if (SplitBefore->getParent() != MBB || SplitCond->getParent() != MBB)
122 if (MIToDelete && MIToDelete->getParent() != MBB)
124 if (NewCond && NewCond->getParent() != MBB)
143 MachineBasicBlock *ThisMBB = BSI.OrigBranch->getParent();
506 if (UseMI.getParent() != MIParam.getParent())
506 if (UseMI.getParent() != MIParam.getParent())
514 (MIParam.getParent() == Ret.TrueDefs.first->getParent());
514 (MIParam.getParent() == Ret.TrueDefs.first->getParent());
517 (MIParam.getParent() == Ret.TrueDefs.second->getParent());
517 (MIParam.getParent() == Ret.TrueDefs.second->getParent());
558 MachineBasicBlock::iterator Me = Copy, B = Copy->getParent()->begin();
643 for (auto E = CRI.MI->getParent()->end(); Def2It != E; ++Def2It) {
652 LLVM_DEBUG(CRI.MI->getParent()->dump());
663 MachineBasicBlock *MBB = SplitBefore->getParent();
lib/Target/PowerPC/PPCRegisterInfo.cpp 497 MachineBasicBlock &MBB = *MI.getParent();
616 MachineBasicBlock &MBB = *MI.getParent();
647 MachineBasicBlock &MBB = *MI.getParent();
692 MachineBasicBlock &MBB = *MI.getParent();
735 MachineBasicBlock &MBB = *MI.getParent();
815 MachineBasicBlock &MBB = *MI.getParent();
865 MachineBasicBlock &MBB = *MI.getParent();
891 MachineBasicBlock &MBB = *MI.getParent();
991 MachineBasicBlock &MBB = *MI.getParent();
1196 MachineBasicBlock &MBB = *MI->getParent();
1255 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 121 if (!AddendMI || AddendMI->getParent() != MI.getParent())
121 if (!AddendMI || AddendMI->getParent() != MI.getParent())
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 802 BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
916 BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
924 BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
950 MachineBasicBlock *MBB = MI->getParent();
977 dbgs() << format(" %bb.%3d", MI->getParent()->getNumber());
lib/Target/RISCV/RISCVRegisterInfo.cpp 108 MachineFunction &MF = *MI.getParent()->getParent();
124 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/Sparc/SparcInstrInfo.cpp 502 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
lib/Target/Sparc/SparcRegisterInfo.cpp 132 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
137 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
150 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
152 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
155 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
172 MachineFunction &MF = *MI.getParent()->getParent();
189 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
201 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
lib/Target/SystemZ/SystemZElimCompare.cpp 235 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
278 MachineInstrBuilder(*Branch->getParent()->getParent(), Branch)
299 auto MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(Opcode));
386 MachineBasicBlock::iterator MBBI = MI, MBBE = MI.getParent()->end();
430 MachineBasicBlock &MBB = *Compare.getParent();
563 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
lib/Target/SystemZ/SystemZISelLowering.cpp 6507 MachineBasicBlock *MBB = MI.getParent();
lib/Target/SystemZ/SystemZInstrBuilder.h 28 MachineFunction &MF = *MI->getParent()->getParent();
lib/Target/SystemZ/SystemZInstrInfo.cpp 67 MachineBasicBlock *MBB = MI->getParent();
117 MachineBasicBlock *MBB = MI->getParent();
162 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
200 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
212 MachineBasicBlock *MBB = MI->getParent();
278 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
727 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
734 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
745 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
757 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
950 MachineBasicBlock *MBB = MI.getParent();
1020 MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1048 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1063 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1078 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1093 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1104 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1131 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1142 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1191 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
lib/Target/SystemZ/SystemZLDCleanup.cpp 119 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
139 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
lib/Target/SystemZ/SystemZLongBranch.cpp 356 MachineBasicBlock *MBB = MI->getParent();
375 MachineBasicBlock *MBB = MI->getParent();
lib/Target/SystemZ/SystemZMachineScheduler.cpp 64 ((LastEmittedMI != nullptr && LastEmittedMI->getParent() == MBB) ?
lib/Target/SystemZ/SystemZPostRewrite.cpp 122 BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
129 BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
lib/Target/SystemZ/SystemZRegisterInfo.cpp 257 MachineBasicBlock &MBB = *MI->getParent();
361 MachineBasicBlock *MBB = MI->getParent();
368 if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
369 (!FirstMI_GRNar || FirstMI_GRNar->getParent() != MBB) ||
370 (!LastMI_GR128 || LastMI_GR128->getParent() != MBB) ||
371 (!LastMI_GRNar || LastMI_GRNar->getParent() != MBB))
lib/Target/SystemZ/SystemZShortenInst.cpp 146 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
169 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 271 auto *LoopBottom = BeginToEnd[&MI]->getParent()->getPrevNode();
350 if (EndToBegin[&MI]->getParent()->getNumber() >= Header->getNumber())
502 auto *LoopBottom = BeginToEnd[&MI]->getParent()->getPrevNode();
604 if (EndToBegin[&MI]->getParent()->getNumber() > Header->getNumber())
662 MachineBasicBlock *Cont = BeginToEnd[EHPadToTry[&MBB]]->getParent();
687 MachineBasicBlock *TryBB = Try->getParent();
688 MachineBasicBlock *Cont = EndTry->getParent();
719 if (Def->getParent() == &MBB)
877 EHPadStack.push_back(MI.getParent());
918 EHPadStack.push_back(MI.getParent());
1032 MachineBasicBlock *Cont = EndTry->getParent();
1111 auto *MBB = RangeBegin->getParent();
1181 ScopeTops[MBB.getNumber()] = EndToBegin[&MI]->getParent();
1184 ScopeTops[MBB.getNumber()] = EHPadToTry[&MBB]->getParent();
1323 Stack.push_back(EndToBegin[&MI]->getParent());
lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp 26 MachineBasicBlock *MBB = Insert->getParent();
28 MBB->splice(Insert, DBI->getParent(), DBI);
38 MachineBasicBlock *MBB = Insert->getParent();
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 91 *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
224 MachineFunction &MF = *Cond[1].getParent()->getParent()->getParent();
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 61 MachineFunction *MF = MI->getParent()->getParent();
64 WL.push_back(MI->getParent());
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 126 MachineInstr *Const = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
856 bool SameBlock = Def->getParent() == &MBB;
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 59 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 342 E = LoadInst->getParent()->rend();
359 MachineBasicBlock *MBB = LoadInst->getParent();
390 MachineBasicBlock *MBB = LoadInst->getParent();
502 LoadInst->getParent()->instr_begin()).getNodePtr();
549 if (StoreMI.getParent() == MI.getParent() &&
549 if (StoreMI.getParent() == MI.getParent() &&
566 *LoadInst->getParent()->getParent());
lib/Target/X86/X86AvoidTrailingCall.cpp 101 BuildMI(*LastRealInstr->getParent(), MBBI, LastRealInstr->getDebugLoc(),
lib/Target/X86/X86CallFrameOptimization.cpp 499 MachineBasicBlock &MBB = *(FrameSetup->getParent());
624 DefMI.getParent() != FrameSetup->getParent())
624 DefMI.getParent() != FrameSetup->getParent())
lib/Target/X86/X86CmovConversion.cpp 570 MachineBasicBlock *BB = MI->getParent();
605 MachineBasicBlock *MBB = First->getParent();
664 MachineBasicBlock *MBB = MI.getParent();
lib/Target/X86/X86DomainReassignment.cpp 155 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(DstOpcode));
182 MachineBasicBlock *MBB = MI->getParent();
270 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
lib/Target/X86/X86ExpandPseudo.cpp 277 NewMI.copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
lib/Target/X86/X86FixupSetCC.cpp 120 MI.getParent(), MachineBasicBlock::reverse_iterator(&MI));
148 BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
lib/Target/X86/X86FlagsCopyLowering.cpp 242 assert(SplitI.getParent() == &MBB &&
365 MachineBasicBlock &MBB = *CopyI->getParent();
408 MachineBasicBlock *TestMBB = CopyDefI.getParent();
687 if (JmpI->getParent() == LastJmpMBB)
688 splitBlock(*JmpI->getParent(), *JmpI, *TII);
690 LastJmpMBB = JmpI->getParent();
814 MachineBasicBlock &MBB = *MI.getParent();
842 MachineBasicBlock &MBB = *CMovI.getParent();
865 MachineBasicBlock &JmpMBB = *JmpI.getParent();
911 MachineBasicBlock &MBB = *SetBI.getParent();
1035 auto MIB = BuildMI(*SetCCI.getParent(), SetCCI.getIterator(),
lib/Target/X86/X86FloatingPoint.cpp 975 const MachineFunction* MF = I->getParent()->getParent();
lib/Target/X86/X86InstrBuilder.h 200 MachineFunction &MF = *MI->getParent()->getParent();
lib/Target/X86/X86InstrInfo.cpp 707 MachineFunction &MF = *MI.getParent()->getParent();
745 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
900 MachineFunction &MF = *MI.getParent()->getParent();
1532 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1577 if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
3615 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
3615 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
3658 RE = CmpInstr.getParent() == MI->getParent()
3658 RE = CmpInstr.getParent() == MI->getParent()
3660 : CmpInstr.getParent()->rend();
3703 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3786 MachineBasicBlock *MBB = CmpInstr.getParent();
3799 InsertE = Sub->getParent()->rend();
3804 Sub->getParent()->remove(Movr0Inst);
3805 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3908 MachineBasicBlock &MBB = *MIB->getParent();
3927 MachineBasicBlock &MBB = *MIB->getParent();
3984 MachineBasicBlock &MBB = *MIB->getParent();
4005 MachineBasicBlock &MBB = *MIB->getParent();
4079 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4578 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4586 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4595 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4601 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4683 MachineBasicBlock *MBB = InsertPt->getParent();
4711 MachineBasicBlock *MBB = InsertPt->getParent();
4721 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
7900 MachineFunction *MF = I.getParent()->getParent();
7907 BuildMI(*I.getParent(), I, I.getDebugLoc(),
7920 MachineFunction *MF = I.getParent()->getParent();
7934 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8064 if (MI.getParent()->succ_empty())
lib/Target/X86/X86InstructionSelector.cpp 253 BuildMI(*I.getParent(), I, I.getDebugLoc(),
308 assert(I.getParent() && "Instruction should be in a basic block!");
309 assert(I.getParent()->getParent() && "Instruction should be in a function!");
311 MachineBasicBlock &MBB = *I.getParent();
829 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ZextEntryIt->MovOp))
834 BuildMI(*I.getParent(), I, I.getDebugLoc(),
863 BuildMI(*I.getParent(), I, I.getDebugLoc(),
871 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg)
925 BuildMI(*I.getParent(), I, I.getDebugLoc(),
973 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
977 MachineInstr &SetInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1033 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
1039 MachineInstr &Set1 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1041 MachineInstr &Set2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1043 MachineInstr &Set3 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1066 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
1071 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
1105 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), X86::EFLAGS)
1122 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg)
1126 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg)
1226 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg)
1263 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY))
1340 *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1379 MachineInstr &InsertInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1391 MachineInstr &CopyInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1411 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
1414 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JCC_1))
1453 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg)
1461 addDirectMem(BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg),
1479 BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg), CPI, PICBase,
1643 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy),
1649 BuildMI(*I.getParent(), I, I.getDebugLoc(),
1653 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0),
1660 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
1664 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
1668 BuildMI(*I.getParent(), I, I.getDebugLoc(),
1677 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem))
1692 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg)
1696 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri),
1702 BuildMI(*I.getParent(), I, I.getDebugLoc(),
1709 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
1726 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TRAP));
lib/Target/X86/X86OptimizeLEAs.cpp 494 MachineBasicBlock *MBB = (*LEAs.begin()->second.begin())->getParent();
577 MachineBasicBlock *MBB = MI.getParent();
lib/Target/X86/X86RegisterInfo.cpp 696 MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
697 TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
719 MachineBasicBlock &MBB = *MI.getParent();
lib/Target/X86/X86SpeculativeLoadHardening.cpp 1949 MachineBasicBlock &MBB = *MI.getParent();
2202 if (!isDataInvariant(UseMI) || UseMI.getParent() != MI.getParent())
2202 if (!isDataInvariant(UseMI) || UseMI.getParent() != MI.getParent())
2331 MachineBasicBlock &MBB = *MI.getParent();
2382 MachineBasicBlock &MBB = *MI.getParent();
2429 MachineBasicBlock &MBB = *MI.getParent();
2633 OldTargetReg, *MI.getParent(), MI.getIterator(), MI.getDebugLoc());
lib/Target/X86/X86WinAllocaExpander.cpp 199 MachineBasicBlock *MBB = MI->getParent();
lib/Target/XCore/XCoreRegisterInfo.cpp 65 MachineBasicBlock &MBB = *MI.getParent();
98 MachineBasicBlock &MBB = *MI.getParent();
132 MachineBasicBlock &MBB = *MI.getParent();
166 MachineBasicBlock &MBB = *MI.getParent();
267 MachineFunction &MF = *MI.getParent()->getParent();
319 MachineBasicBlock &MBB = *MI.getParent();
unittests/MI/LiveIntervalTest.cpp 125 MachineBasicBlock &MBB = *FromInstr.getParent();